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qma6100p_regs.h File Reference
Drivers » Sensor Device Drivers | Drivers » [S]ensor [A]ctuator [U]ber [L]ayer » QMA6100P 3-axis Accelerometer

Register definitions for the QST QMA6100P accelerometer. More...

Detailed Description

Register definitions for the QST QMA6100P accelerometer.

Author
Baptiste Le Duc bapti.nosp@m.ste..nosp@m.leduc.nosp@m.@eti.nosp@m.k.com
Léandre Le Duc leand.nosp@m.re.l.nosp@m.educ3.nosp@m.8@gm.nosp@m.ail.c.nosp@m.om

Definition in file qma6100p_regs.h.

Go to the source code of this file.

Chip ID register (0x00)

#define QMA6100P_REG_CHIP_ID   (0x00)
 Chip ID.
 

Acceleration data registers (0x01–0x06)

14-bit two's complement, burst-readable LSB[7:2]=data[5:0], LSB[0]=NEWDATA MSB[7:0]=data[13:6], MSB[7]=sign Pairs: DX=0x01-02, DY=0x03-04, DZ=0x05-06

#define QMA6100P_REG_DX_LSB   (0x01)
 X low: data[5:0] in bits[7:2].
 
#define QMA6100P_REG_DX_MSB   (0x02)
 X high: data[13:6].
 
#define QMA6100P_REG_DY_LSB   (0x03)
 Y low.
 
#define QMA6100P_REG_DY_MSB   (0x04)
 Y high.
 
#define QMA6100P_REG_DZ_LSB   (0x05)
 Z low.
 
#define QMA6100P_REG_DZ_MSB   (0x06)
 Z high.
 

Control and configuration registers

#define QMA6100P_REG_RANGE   (0x0F)
 full-scale range + LPF/HPF select
 
#define QMA6100P_REG_ODR   (0x10)
 output data rate + NLPF
 
#define QMA6100P_REG_PM   (0x11)
 power management (MODE, MCLK)
 
#define QMA6100P_REG_SW_RESET   (0x36)
 soft reset
 
#define QMA6100P_REG_NVM   (0x33)
 Non Volatile Memory.
 
#define QMA6100P_REG_CHIP_STATE   (0x45)
 chip state
 
#define QMA6100P_REG_ULPS   (0x46)
 ULPS control register.
 
#define QMA6100P_REG_TST0_ANA   (0x4A)
 analog test register 0
 
#define QMA6100P_REG_AFE_ANA   (0x56)
 analog front-end config
 
#define QMA6100P_REG_TST1_ANA   (0x5F)
 analog test register 1
 

Interrupt registers

#define QMA6100P_REG_INT_ST2   (0x0B)
 interrupt status 2 (FIFO/data)
 
#define QMA6100P_REG_INT_EN1   (0x17)
 interrupt enable register
 
#define QMA6100P_REG_INT1_MAP1   (0x1A)
 INT1 map: no_mot/FIFO/data/q_tap/any_mot.
 
#define QMA6100P_REG_INT2_MAP1   (0x1C)
 INT2 map: no_mot/FIFO/data/q_tap/any_mot.
 
#define QMA6100P_REG_INTPIN_CONF   (0x20)
 INT pin config (OD/LVL)
 
#define QMA6100P_REG_INT_CFG   (0x21)
 interrupt latch/shadow/I2C config
 

CHIP_ID (0x00) masks - chip ID field

Bits[7:4] = 0x9 (fixed).

Bits[3:0] factory-set, software must ignore

#define QMA6100P_CHIP_ID_MASK   (0xF0)
 mask for the fixed upper nibble
 
#define QMA6100P_CHIP_ID_VAL   (0x90)
 expected upper nibble (0x9x), lower nibble is factory-set
 

Data QMA6100P_REG_D(X|Y|Z)_LSB masks - new-data flag

#define QMA6100P_NEWDATA_FLAG_MASK   (1 << 0)
 1 = channel updated since last read
 

INT_ST2 (0x0B) masks - data-ready status

#define QMA6100P_INT_ST2_DATA_INT_MASK   (1 << 4)
 data-ready interrupt active
 

RANGE (0x0F) masks - full-scale range and filter select

#define QMA6100P_RANGE_MASK   (0b00001111)
 full-scale range bits[3:0] mask
 
#define QMA6100P_RANGE_LPF_HPF_MASK   (1 << 6)
 0=LPF mode, 1=HPF mode (affects NLPF in ODR)
 

Resolution - Range associated resolution used to convert in g in ug/LSB

#define QMA6100P_2G_RESOLUTION   (244)
 resolution for a ±2g range
 
#define QMA6100P_4G_RESOLUTION   (488)
 resolution for a ±4g range
 
#define QMA6100P_8G_RESOLUTION   (977)
 resolution for a ±8g range
 
#define QMA6100P_16G_RESOLUTION   (1950)
 resolution for a ±16g range
 
#define QMA6100P_32G_RESOLUTION   (3810)
 resolution for a ±32g range
 

ODR (0x10) masks - output data rate and filter

ODR[4:0] in bits[4:0], NLPF[2:0] in bits[7:5]

NLPF (Numerical Low-Pass Filter) oversampling ratio depends on RANGE[LPF_HPF]:

  • LPF mode: 000=off, 100=×1, x01=×2, x10=×4, x11=×8
  • HPF mode: 000=off, 001=ODR/10, 010=ODR/25, ...
#define QMA6100P_ODR_MASK   (0b00011111)
 ODR bits[4:0] mask.
 
#define QMA6100P_NLPF_MASK   (0b11100000)
 NLPF bits[7:5] mask.
 

PM (0x11) masks - power management

#define QMA6100P_PM_MODE_MASK   (1 << 7)
 active/standby mode bit mask
 
#define QMA6100P_PM_MCLK_MASK   (0b00001111)
 MCLK[3:0].
 

INT_EN1 (0x17) masks - data-ready interrupt enable

#define QMA6100P_INT_EN1_DATA_MASK   (1 << 4)
 data-ready interrupt enable
 

INT1_MAP1 (0x1A) / INT2_MAP1 (0x1C) masks - route data-ready to INT pin

#define QMA6100P_INT_MAP1_DATA_MASK   (1 << 4)
 route data-ready to INTx pin
 

INTPIN_CONF (0x20) masks - INT pin electrical config

Default 0x05 = INT1 active-high push-pull, INT2 active-high push-pull

#define QMA6100P_INTPIN_INT1_LVL_MASK   (1 << 0)
 INT1 active level mask (qma6100p_int_active_level_t)
 
#define QMA6100P_INTPIN_INT1_OD_MASK   (1 << 1)
 INT1 output mode mask (qma6100p_int_pin_mode_t)
 
#define QMA6100P_INTPIN_INT2_LVL_MASK   (1 << 2)
 INT2 active level mask (qma6100p_int_active_level_t)
 
#define QMA6100P_INTPIN_INT2_OD_MASK   (1 << 3)
 INT2 output mode mask (qma6100p_int_pin_mode_t)
 

INT_CFG (0x21) masks - interrupt shadow config

#define QMA6100P_INT_CFG_SHADOW_MASK   (1 << 6)
 data shadowing mode mask (qma6100p_int_shadow_t)
 

INT shadowing function mode

#define QMA6100P_INT_CFG_SHADOW_EN   (0)
 shadowing enabled (default)
 
#define QMA6100P_INT_CFG_SHADOW_DIS   (1)
 shadowing disabled
 

NVM_REGISTER (0x33) - Non Volatile Memory state

#define QMA6100P_NVM_LOAD_DONE   (1 << 0)
 set to 1 when NVM loading is done
 
#define QMA6100P_NVM_RDY   (1 << 2)
 set to 1 when NVM is ready, and programming NVIM is done
 

SW_RESET (0x36)

#define QMA6100P_SW_RESET_VAL   (0xB6)
 trigger soft reset
 

TST1_ANA_REGISTER (0x5F) - Take control mode setting

#define QMA6100P_ANA_TST1_TMODE   (1 << 7)
 bit mask of the tmode
 

Macro Definition Documentation

◆ QMA6100P_16G_RESOLUTION

#define QMA6100P_16G_RESOLUTION   (1950)

resolution for a ±16g range

Definition at line 125 of file qma6100p_regs.h.

◆ QMA6100P_2G_RESOLUTION

#define QMA6100P_2G_RESOLUTION   (244)

resolution for a ±2g range

Definition at line 122 of file qma6100p_regs.h.

◆ QMA6100P_32G_RESOLUTION

#define QMA6100P_32G_RESOLUTION   (3810)

resolution for a ±32g range

Definition at line 126 of file qma6100p_regs.h.

◆ QMA6100P_4G_RESOLUTION

#define QMA6100P_4G_RESOLUTION   (488)

resolution for a ±4g range

Definition at line 123 of file qma6100p_regs.h.

◆ QMA6100P_8G_RESOLUTION

#define QMA6100P_8G_RESOLUTION   (977)

resolution for a ±8g range

Definition at line 124 of file qma6100p_regs.h.

◆ QMA6100P_ANA_TST1_TMODE

#define QMA6100P_ANA_TST1_TMODE   (1 << 7)

bit mask of the tmode

Definition at line 218 of file qma6100p_regs.h.

◆ QMA6100P_CHIP_ID_MASK

#define QMA6100P_CHIP_ID_MASK   (0xF0)

mask for the fixed upper nibble

Definition at line 89 of file qma6100p_regs.h.

◆ QMA6100P_CHIP_ID_VAL

#define QMA6100P_CHIP_ID_VAL   (0x90)

expected upper nibble (0x9x), lower nibble is factory-set

Definition at line 91 of file qma6100p_regs.h.

◆ QMA6100P_INT_CFG_SHADOW_DIS

#define QMA6100P_INT_CFG_SHADOW_DIS   (1)

shadowing disabled

Definition at line 193 of file qma6100p_regs.h.

◆ QMA6100P_INT_CFG_SHADOW_EN

#define QMA6100P_INT_CFG_SHADOW_EN   (0)

shadowing enabled (default)

Definition at line 192 of file qma6100p_regs.h.

◆ QMA6100P_INT_CFG_SHADOW_MASK

#define QMA6100P_INT_CFG_SHADOW_MASK   (1 << 6)

data shadowing mode mask (qma6100p_int_shadow_t)

Definition at line 185 of file qma6100p_regs.h.

◆ QMA6100P_INT_EN1_DATA_MASK

#define QMA6100P_INT_EN1_DATA_MASK   (1 << 4)

data-ready interrupt enable

Definition at line 155 of file qma6100p_regs.h.

◆ QMA6100P_INT_MAP1_DATA_MASK

#define QMA6100P_INT_MAP1_DATA_MASK   (1 << 4)

route data-ready to INTx pin

Definition at line 162 of file qma6100p_regs.h.

◆ QMA6100P_INT_ST2_DATA_INT_MASK

#define QMA6100P_INT_ST2_DATA_INT_MASK   (1 << 4)

data-ready interrupt active

Definition at line 105 of file qma6100p_regs.h.

◆ QMA6100P_INTPIN_INT1_LVL_MASK

#define QMA6100P_INTPIN_INT1_LVL_MASK   (1 << 0)

INT1 active level mask (qma6100p_int_active_level_t)

Definition at line 171 of file qma6100p_regs.h.

◆ QMA6100P_INTPIN_INT1_OD_MASK

#define QMA6100P_INTPIN_INT1_OD_MASK   (1 << 1)

INT1 output mode mask (qma6100p_int_pin_mode_t)

Definition at line 173 of file qma6100p_regs.h.

◆ QMA6100P_INTPIN_INT2_LVL_MASK

#define QMA6100P_INTPIN_INT2_LVL_MASK   (1 << 2)

INT2 active level mask (qma6100p_int_active_level_t)

Definition at line 175 of file qma6100p_regs.h.

◆ QMA6100P_INTPIN_INT2_OD_MASK

#define QMA6100P_INTPIN_INT2_OD_MASK   (1 << 3)

INT2 output mode mask (qma6100p_int_pin_mode_t)

Definition at line 177 of file qma6100p_regs.h.

◆ QMA6100P_NEWDATA_FLAG_MASK

#define QMA6100P_NEWDATA_FLAG_MASK   (1 << 0)

1 = channel updated since last read

Definition at line 98 of file qma6100p_regs.h.

◆ QMA6100P_NLPF_MASK

#define QMA6100P_NLPF_MASK   (0b11100000)

NLPF bits[7:5] mask.

Definition at line 140 of file qma6100p_regs.h.

◆ QMA6100P_NVM_LOAD_DONE

#define QMA6100P_NVM_LOAD_DONE   (1 << 0)

set to 1 when NVM loading is done

Definition at line 202 of file qma6100p_regs.h.

◆ QMA6100P_NVM_RDY

#define QMA6100P_NVM_RDY   (1 << 2)

set to 1 when NVM is ready, and programming NVIM is done

Definition at line 204 of file qma6100p_regs.h.

◆ QMA6100P_ODR_MASK

#define QMA6100P_ODR_MASK   (0b00011111)

ODR bits[4:0] mask.

Definition at line 139 of file qma6100p_regs.h.

◆ QMA6100P_PM_MCLK_MASK

#define QMA6100P_PM_MCLK_MASK   (0b00001111)

MCLK[3:0].

Definition at line 148 of file qma6100p_regs.h.

◆ QMA6100P_PM_MODE_MASK

#define QMA6100P_PM_MODE_MASK   (1 << 7)

active/standby mode bit mask

Definition at line 147 of file qma6100p_regs.h.

◆ QMA6100P_RANGE_LPF_HPF_MASK

#define QMA6100P_RANGE_LPF_HPF_MASK   (1 << 6)

0=LPF mode, 1=HPF mode (affects NLPF in ODR)

Definition at line 115 of file qma6100p_regs.h.

◆ QMA6100P_RANGE_MASK

#define QMA6100P_RANGE_MASK   (0b00001111)

full-scale range bits[3:0] mask

Definition at line 113 of file qma6100p_regs.h.

◆ QMA6100P_REG_AFE_ANA

#define QMA6100P_REG_AFE_ANA   (0x56)

analog front-end config

Definition at line 66 of file qma6100p_regs.h.

◆ QMA6100P_REG_CHIP_ID

#define QMA6100P_REG_CHIP_ID   (0x00)

Chip ID.

Definition at line 33 of file qma6100p_regs.h.

◆ QMA6100P_REG_CHIP_STATE

#define QMA6100P_REG_CHIP_STATE   (0x45)

chip state

Definition at line 63 of file qma6100p_regs.h.

◆ QMA6100P_REG_DX_LSB

#define QMA6100P_REG_DX_LSB   (0x01)

X low: data[5:0] in bits[7:2].

Definition at line 46 of file qma6100p_regs.h.

◆ QMA6100P_REG_DX_MSB

#define QMA6100P_REG_DX_MSB   (0x02)

X high: data[13:6].

Definition at line 47 of file qma6100p_regs.h.

◆ QMA6100P_REG_DY_LSB

#define QMA6100P_REG_DY_LSB   (0x03)

Y low.

Definition at line 48 of file qma6100p_regs.h.

◆ QMA6100P_REG_DY_MSB

#define QMA6100P_REG_DY_MSB   (0x04)

Y high.

Definition at line 49 of file qma6100p_regs.h.

◆ QMA6100P_REG_DZ_LSB

#define QMA6100P_REG_DZ_LSB   (0x05)

Z low.

Definition at line 50 of file qma6100p_regs.h.

◆ QMA6100P_REG_DZ_MSB

#define QMA6100P_REG_DZ_MSB   (0x06)

Z high.

Definition at line 51 of file qma6100p_regs.h.

◆ QMA6100P_REG_INT1_MAP1

#define QMA6100P_REG_INT1_MAP1   (0x1A)

INT1 map: no_mot/FIFO/data/q_tap/any_mot.

Definition at line 76 of file qma6100p_regs.h.

◆ QMA6100P_REG_INT2_MAP1

#define QMA6100P_REG_INT2_MAP1   (0x1C)

INT2 map: no_mot/FIFO/data/q_tap/any_mot.

Definition at line 77 of file qma6100p_regs.h.

◆ QMA6100P_REG_INT_CFG

#define QMA6100P_REG_INT_CFG   (0x21)

interrupt latch/shadow/I2C config

Definition at line 79 of file qma6100p_regs.h.

◆ QMA6100P_REG_INT_EN1

#define QMA6100P_REG_INT_EN1   (0x17)

interrupt enable register

Definition at line 75 of file qma6100p_regs.h.

◆ QMA6100P_REG_INT_ST2

#define QMA6100P_REG_INT_ST2   (0x0B)

interrupt status 2 (FIFO/data)

Definition at line 74 of file qma6100p_regs.h.

◆ QMA6100P_REG_INTPIN_CONF

#define QMA6100P_REG_INTPIN_CONF   (0x20)

INT pin config (OD/LVL)

Definition at line 78 of file qma6100p_regs.h.

◆ QMA6100P_REG_NVM

#define QMA6100P_REG_NVM   (0x33)

Non Volatile Memory.

Definition at line 62 of file qma6100p_regs.h.

◆ QMA6100P_REG_ODR

#define QMA6100P_REG_ODR   (0x10)

output data rate + NLPF

Definition at line 59 of file qma6100p_regs.h.

◆ QMA6100P_REG_PM

#define QMA6100P_REG_PM   (0x11)

power management (MODE, MCLK)

Definition at line 60 of file qma6100p_regs.h.

◆ QMA6100P_REG_RANGE

#define QMA6100P_REG_RANGE   (0x0F)

full-scale range + LPF/HPF select

Definition at line 58 of file qma6100p_regs.h.

◆ QMA6100P_REG_SW_RESET

#define QMA6100P_REG_SW_RESET   (0x36)

soft reset

Definition at line 61 of file qma6100p_regs.h.

◆ QMA6100P_REG_TST0_ANA

#define QMA6100P_REG_TST0_ANA   (0x4A)

analog test register 0

Definition at line 65 of file qma6100p_regs.h.

◆ QMA6100P_REG_TST1_ANA

#define QMA6100P_REG_TST1_ANA   (0x5F)

analog test register 1

Definition at line 67 of file qma6100p_regs.h.

◆ QMA6100P_REG_ULPS

#define QMA6100P_REG_ULPS   (0x46)

ULPS control register.

Definition at line 64 of file qma6100p_regs.h.

◆ QMA6100P_SW_RESET_VAL

#define QMA6100P_SW_RESET_VAL   (0xB6)

trigger soft reset

Definition at line 211 of file qma6100p_regs.h.