periph_cpu.h

Go to the documentation of this file.

/*
 * Copyright (C) 2019 ML!PA Consulting GmbH
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <limits.h>
 
#include "macros/units.h"
#include "periph_cpu_common.h"
 
#include "candev_samd5x.h"
#ifdef __cplusplus
extern "C" {
#endif
 
#define SAM0_DFLL_FREQ_HZ       MHZ(48)
 
#define SAM0_XOSC_FREQ_HZ       (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)
 
#define SAM0_DPLL_FREQ_MIN_HZ   MHZ(96)
 
#define SAM0_DPLL_FREQ_MAX_HZ   MHZ(200)
 
#define PM_NUM_MODES            (4)     
enum {
    SAM0_PM_BACKUP = 0,
    SAM0_PM_HIBERNATE = 1,
    SAM0_PM_STANDBY = 2,
    SAM0_PM_IDLE = 3,
};
#define SAM0_GCLK_MAIN 0                
#ifndef SAM0_GCLK_32KHZ
#define SAM0_GCLK_32KHZ 1               
#endif
#ifndef SAM0_GCLK_TIMER
#define SAM0_GCLK_TIMER 2               
#endif
#ifndef SAM0_GCLK_PERIPH
#define SAM0_GCLK_PERIPH 3              
#endif
#ifndef SAM0_GCLK_100MHZ
#define SAM0_GCLK_100MHZ 4              
#endif
#define SAM0_GCLK_8MHZ      SAM0_GCLK_TIMER
#define SAM0_GCLK_48MHZ     SAM0_GCLK_PERIPH
#define SPI_HWCS(x)     (UINT_MAX - 1)
 
static const gpio_t sam0_adc_pins[2][16] = {
    {   /* ADC0 pins */
        GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8),  GPIO_PIN(PB, 9),
        GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6),  GPIO_PIN(PA, 7),
        GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
        GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2),  GPIO_PIN(PB, 3)
    },
    {   /* ADC1 pins */
        GPIO_PIN(PB, 8),  GPIO_PIN(PB, 9),  GPIO_PIN(PA, 8), GPIO_PIN(PA, 9),
        GPIO_PIN(PC, 2),  GPIO_PIN(PC, 3),  GPIO_PIN(PB, 4), GPIO_PIN(PB, 5),
        GPIO_PIN(PB, 6),  GPIO_PIN(PB, 7),  GPIO_PIN(PC, 0), GPIO_PIN(PC, 1),
        GPIO_PIN(PC, 30), GPIO_PIN(PC, 31), GPIO_PIN(PD, 0), GPIO_PIN(PD, 1)
    }
};
 
#define ADC0_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC0_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC0_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC0_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC0_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC0_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC0_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC0_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN7 
#define ADC0_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN8 
#define ADC0_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN9 
#define ADC0_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN10 
#define ADC0_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN11 
#define ADC0_INPUTCTRL_MUXPOS_PB00 ADC_INPUTCTRL_MUXPOS_AIN12 
#define ADC0_INPUTCTRL_MUXPOS_PB01 ADC_INPUTCTRL_MUXPOS_AIN13 
#define ADC0_INPUTCTRL_MUXPOS_PB02 ADC_INPUTCTRL_MUXPOS_AIN14 
#define ADC0_INPUTCTRL_MUXPOS_PB03 ADC_INPUTCTRL_MUXPOS_AIN15 
#define ADC1_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC1_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC1_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC1_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC1_INPUTCTRL_MUXPOS_PC02 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC1_INPUTCTRL_MUXPOS_PC03 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC1_INPUTCTRL_MUXPOS_PB04 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC1_INPUTCTRL_MUXPOS_PB05 ADC_INPUTCTRL_MUXPOS_AIN7 
#define ADC1_INPUTCTRL_MUXPOS_PB06 ADC_INPUTCTRL_MUXPOS_AIN8 
#define ADC1_INPUTCTRL_MUXPOS_PB07 ADC_INPUTCTRL_MUXPOS_AIN9 
#define ADC1_INPUTCTRL_MUXPOS_PC00 ADC_INPUTCTRL_MUXPOS_AIN10 
#define ADC1_INPUTCTRL_MUXPOS_PC01 ADC_INPUTCTRL_MUXPOS_AIN11 
#define ADC1_INPUTCTRL_MUXPOS_PC30 ADC_INPUTCTRL_MUXPOS_AIN12 
#define ADC1_INPUTCTRL_MUXPOS_PC31 ADC_INPUTCTRL_MUXPOS_AIN13 
#define ADC1_INPUTCTRL_MUXPOS_PD00 ADC_INPUTCTRL_MUXPOS_AIN14 
#define ADC1_INPUTCTRL_MUXPOS_PD01 ADC_INPUTCTRL_MUXPOS_AIN15 
#define ADC0_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC0_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC0_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC0_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC0_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC0_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC0_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC0_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN7 
#define ADC1_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC1_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC1_INPUTCTRL_MUXNEG_PA08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC1_INPUTCTRL_MUXNEG_PA09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC1_INPUTCTRL_MUXNEG_PC02 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC1_INPUTCTRL_MUXNEG_PC03 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC1_INPUTCTRL_MUXNEG_PB04 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC1_INPUTCTRL_MUXNEG_PB05 ADC_INPUTCTRL_MUXPOS_AIN7 
#define DAC_RES_BITS        (12)
 
#define DAC_NUMOF           (2)
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                      /* in Hz */
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY)         /* in Hz */
static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
    GPIO_PIN(PB, 0), GPIO_PIN(PB, 2), GPIO_PIN(PA, 2),
    GPIO_PIN(PC, 0), GPIO_PIN(PC, 1)
};
 
static const gpio_t gclk_io_pins[] = {
    GPIO_PIN(PA, 10), GPIO_PIN(PA, 11), GPIO_PIN(PA, 14),
    GPIO_PIN(PA, 15), GPIO_PIN(PA, 16), GPIO_PIN(PA, 17),
    GPIO_PIN(PA, 27), GPIO_PIN(PA, 30), GPIO_PIN(PB, 10),
    GPIO_PIN(PB, 11), GPIO_PIN(PB, 12), GPIO_PIN(PB, 13),
    GPIO_PIN(PB, 14), GPIO_PIN(PB, 15), GPIO_PIN(PB, 16),
    GPIO_PIN(PB, 17), GPIO_PIN(PB, 18), GPIO_PIN(PB, 19),
    GPIO_PIN(PB, 20), GPIO_PIN(PB, 21), GPIO_PIN(PB, 22),
    GPIO_PIN(PB, 23)
};
 
static const uint8_t gclk_io_ids[] = {
    4, 5, 0, 1, 2, 3, 1, 0, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1
};
 
struct sam0_aux_cfg_mapping {
    /* config word 0 */
    uint32_t bod33_disable              :  1; 
    uint32_t bod33_level                :  8; 
    uint32_t bod33_action               :  2; 
    uint32_t bod33_hysteresis           :  4; 
    const uint32_t bod12_calibration    : 11; 
    uint32_t nvm_boot_size              :  4; 
    uint32_t reserved_0                 :  2; 
    /* config word 1 */
    uint32_t smart_eeprom_blocks        :  4; 
    uint32_t smart_eeprom_page_size     :  3; 
    uint32_t ram_eccdis                 :  1; 
    uint32_t reserved_1                 :  8; 
    uint32_t wdt_enable                 :  1; 
    uint32_t wdt_always_on              :  1; 
    uint32_t wdt_period                 :  4; 
    uint32_t wdt_window                 :  4; 
    uint32_t wdt_ewoffset               :  4; 
    uint32_t wdt_window_enable          :  1; 
    uint32_t reserved_2                 :  1; 
    /* config word 2 */
    uint32_t nvm_locks;                       
    /* config word 3 */
    uint32_t user_page;                       
    /* config word 4 */
    uint32_t reserved_3;                      
    /* config words 5,6,7 */
    uint32_t user_pages[3];                   
};
 
#define SAM0_QSPI_PIN_CLK       GPIO_PIN(PB, 10)    
#define SAM0_QSPI_PIN_CS        GPIO_PIN(PB, 11)    
#define SAM0_QSPI_PIN_DATA_0    GPIO_PIN(PA,  8)    
#define SAM0_QSPI_PIN_DATA_1    GPIO_PIN(PA,  9)    
#define SAM0_QSPI_PIN_DATA_2    GPIO_PIN(PA, 10)    
#define SAM0_QSPI_PIN_DATA_3    GPIO_PIN(PA, 11)    
#define SAM0_QSPI_MUX           GPIO_MUX_H          
#define SAM0_SDHC_MUX           GPIO_MUX_I          
#define SAM0_SDHC0_PIN_SDCMD    GPIO_PIN(PA,  8)    
#define SAM0_SDHC0_PIN_SDDAT0   GPIO_PIN(PA,  9)    
#define SAM0_SDHC0_PIN_SDDAT1   GPIO_PIN(PA, 10)    
#define SAM0_SDHC0_PIN_SDDAT2   GPIO_PIN(PA, 11)    
#define SAM0_SDHC0_PIN_SDDAT3   GPIO_PIN(PB, 10)    
#define SAM0_SDHC0_PIN_SDCK     GPIO_PIN(PB, 11)    
#define SAM0_SDHC1_PIN_SDCMD    GPIO_PIN(PA, 20)    
#define SAM0_SDHC1_PIN_SDDAT0   GPIO_PIN(PB, 18)    
#define SAM0_SDHC1_PIN_SDDAT1   GPIO_PIN(PB, 19)    
#define SAM0_SDHC1_PIN_SDDAT2   GPIO_PIN(PB, 20)    
#define SAM0_SDHC1_PIN_SDDAT3   GPIO_PIN(PB, 21)    
#define SAM0_SDHC1_PIN_SDCK     GPIO_PIN(PA, 21)    
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */