Implementation specific CPU configuration options. More...

Detailed Description

Implementation specific CPU configuration options.

Author: Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de; Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file cpu_conf.h.

#include <stdint.h>
#include "cpu_conf_common.h"
#include "stm32_irqs.h"

Include dependency graph for cpu_conf.h:

#define	CORTEXM_ISB_REQUIRED_AFTER_WFI 1
	Enable workaround for bug in WFI by issuing a NOP and an ISB.

#define	CPU_DEFAULT_IRQ_PRIO (1U)
	ARM Cortex-M specific CPU configuration.

#define	CPU_FLASH_BASE FLASH_BASE

#define	FLASHPAGE_WRITE_BLOCK_SIZE (2U)
	Flash page configuration.

#define	FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)

typedef uint16_t	stm32_flashpage_block_t

Macro Definition Documentation

◆ CORTEXM_ISB_REQUIRED_AFTER_WFI

#define CORTEXM_ISB_REQUIRED_AFTER_WFI 1

Enable workaround for bug in WFI by issuing a NOP and an ISB.

This works around a bug on STM32 systems, see 1 for details, or 2 for an archive.org backup. The NOP is required on the STM32L1 when any of the DBG_SLEEP, DBG_STOP or DBG_STANDBY bits in DBGMCU_CR are set 3 and 4.

Definition at line 49 of file cpu_conf.h.

◆ CPU_DEFAULT_IRQ_PRIO

#define CPU_DEFAULT_IRQ_PRIO (1U)

ARM Cortex-M specific CPU configuration.

Definition at line 55 of file cpu_conf.h.

◆ CPU_FLASH_BASE

#define CPU_FLASH_BASE FLASH_BASE

Definition at line 58 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_ALIGNMENT

#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)

Definition at line 201 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_SIZE

#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)

Flash page configuration.

Definition at line 190 of file cpu_conf.h.

Typedef Documentation

◆ stm32_flashpage_block_t

typedef uint16_t stm32_flashpage_block_t

Definition at line 191 of file cpu_conf.h.