Loading...
Searching...
No Matches
cpu_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2016 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21#include "cpu_conf_common.h"
22
23#if defined(CPU_LINE_STM32MP157Cxx)
24#include "vendor/stm32mp157cxx_cm4.h"
25#else
26#include "stm32_irqs.h"
27#endif
28
29/* add unused backup RAM as extra heap */
30#if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
31#define NUM_HEAPS 2
32#endif
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
49#define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
50
55#define CPU_DEFAULT_IRQ_PRIO (1U)
56/* STM32MP1 family has no flash */
57#if !defined(CPU_FAM_STM32MP1)
58#define CPU_FLASH_BASE FLASH_BASE
59#endif
60
61/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
62#if defined(CPU_MODEL_STM32MP157CAC)
63#define CPU_IRQ_NUMOF (150U)
64#endif
66
67/* Provide a CPU_IRQ_NUMOF for STM32H7 family ---
68 * The H7 family typically exposes up to 150 maskable interrupt lines
69 * (NVIC external interrupts). Defining this prevents undefined behavior
70 * where code expects CPU_IRQ_NUMOF to be present.
71 * NOTE: we only add this define; existing logic is left untouched.
72 */
73#if defined(CPU_FAM_STM32H7) && !defined(CPU_IRQ_NUMOF)
74# define CPU_IRQ_NUMOF (150U)
75#endif
76
81#if defined(CPU_FAM_STM32U5)
82#define FLASHPAGE_SIZE (8192U)
83#elif defined(CPU_FAM_STM32WB)
84#define FLASHPAGE_SIZE (4096U)
85#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
86 || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
87 || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
88 || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
89 || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
90 || defined(CPU_FAM_STM32C0)
91#define FLASHPAGE_SIZE (2048U)
92#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
93 || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
94 || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
95 || defined(CPU_LINE_STM32F031x6)
96#define FLASHPAGE_SIZE (1024U)
97#elif defined(CPU_FAM_STM32L1)
98#define FLASHPAGE_SIZE (256U)
99#elif defined(CPU_FAM_STM32L0)
100#define FLASHPAGE_SIZE (128U)
101#endif
102
103#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
104#define FLASHPAGE_ERASE_STATE (0x00U)
105#endif
106
107#ifdef FLASHPAGE_SIZE
108#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
109#endif
110
111#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
112 defined(CPU_FAM_STM32F7)
113#define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
114#define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
115
127#if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
128#define FLASHPAGE_DUAL_BANK 1
129#else
130#define FLASHPAGE_DUAL_BANK 0
131#endif
132
133/* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
134#if defined(CPU_FAM_STM32F7)
135#if defined(CPU_LINE_STM32F745xx) || \
136 defined(CPU_LINE_STM32F746xx) || \
137 defined(CPU_LINE_STM32F750xx) || \
138 defined(CPU_LINE_STM32F756xx) || \
139 defined(CPU_LINE_STM32F765xx) || \
140 defined(CPU_LINE_STM32F767xx) || \
141 defined(CPU_LINE_STM32F769xx) || \
142 defined(CPU_LINE_STM32F777xx) || \
143 defined(CPU_LINE_STM32F779xx)
144#define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
145#elif defined(CPU_LINE_STM32F722xx) || \
146 defined(CPU_LINE_STM32F723xx) || \
147 defined(CPU_LINE_STM32F730xx) || \
148 defined(CPU_LINE_STM32F732xx) || \
149 defined(CPU_LINE_STM32F733xx)
150#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
151#else
152/* Intentionally error on an unknown line to prevent flashpage errors */
153#error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
154#endif
155
156#else /* CPU_FAM_STM32F7 */
157#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
158#endif
159
160#if FLASHPAGE_DUAL_BANK
161/* Number of "large" sectors + 4 for the small sectors that together equal a
162 * single large sector. Times two to account for the two banks */
163#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
164 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
165#else
166/* Number of "large" sectors + 4 for the small sectors that together equal a
167 * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
168 * sectors */
169#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
170 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
171#endif
172
173#endif
174
175/* The minimum block size which can be written depends on the family.
176 * However, the erase block is always FLASHPAGE_SIZE.
177 */
178#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
179 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
180 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
181 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
182#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
183typedef uint64_t stm32_flashpage_block_t;
184#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
185 defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
186 defined(CPU_FAM_STM32F7)
187#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
188typedef uint32_t stm32_flashpage_block_t;
189#else
190#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
191typedef uint16_t stm32_flashpage_block_t;
192#endif
193
194#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
195 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
196 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
197 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
198#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
199#else
200/* Writing should be always 4 bytes aligned */
201#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
202#endif
204
209#ifdef SRAM_BB_BASE
210#define CPU_HAS_BITBAND 1
211#endif
213
214#ifdef __cplusplus
215}
216#endif
217