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cpu_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2016 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21#include "cpu_conf_common.h"
22
23#if defined(CPU_LINE_STM32F030x4)
24#include "vendor/stm32f030x4.h"
25#elif defined(CPU_LINE_STM32MP157Cxx)
26#include "vendor/stm32mp157cxx_cm4.h"
27#else
28#include "stm32_irqs.h"
29#endif
30
31/* add unused backup RAM as extra heap */
32#if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
33#define NUM_HEAPS 2
34#endif
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
48#define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
49
54#define CPU_DEFAULT_IRQ_PRIO (1U)
55/* STM32MP1 family has no flash */
56#if !defined(CPU_FAM_STM32MP1)
57#define CPU_FLASH_BASE FLASH_BASE
58#endif
59
60/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
61#if defined(CPU_LINE_STM32F030x4)
62#define CPU_IRQ_NUMOF (28U)
63#elif defined(CPU_MODEL_STM32MP157CAC)
64#define CPU_IRQ_NUMOF (150U)
65#endif
67
68/* Provide a CPU_IRQ_NUMOF for STM32H7 family ---
69 * The H7 family typically exposes up to 150 maskable interrupt lines
70 * (NVIC external interrupts). Defining this prevents undefined behavior
71 * where code expects CPU_IRQ_NUMOF to be present.
72 * NOTE: we only add this define; existing logic is left untouched.
73 */
74#if defined(CPU_FAM_STM32H7) && !defined(CPU_IRQ_NUMOF)
75# define CPU_IRQ_NUMOF (150U)
76#endif
77
82#if defined(CPU_FAM_STM32U5)
83#define FLASHPAGE_SIZE (8192U)
84#elif defined(CPU_FAM_STM32WB)
85#define FLASHPAGE_SIZE (4096U)
86#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
87 || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
88 || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
89 || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
90 || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
91 || defined(CPU_FAM_STM32C0)
92#define FLASHPAGE_SIZE (2048U)
93#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
94 || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
95 || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
96 || defined(CPU_LINE_STM32F031x6)
97#define FLASHPAGE_SIZE (1024U)
98#elif defined(CPU_FAM_STM32L1)
99#define FLASHPAGE_SIZE (256U)
100#elif defined(CPU_FAM_STM32L0)
101#define FLASHPAGE_SIZE (128U)
102#endif
103
104#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
105#define FLASHPAGE_ERASE_STATE (0x00U)
106#endif
107
108#ifdef FLASHPAGE_SIZE
109#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
110#endif
111
112#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
113 defined(CPU_FAM_STM32F7)
114#define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
115#define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
116
128#if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
129#define FLASHPAGE_DUAL_BANK 1
130#else
131#define FLASHPAGE_DUAL_BANK 0
132#endif
133
134/* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
135#if defined(CPU_FAM_STM32F7)
136#if defined(CPU_LINE_STM32F745xx) || \
137 defined(CPU_LINE_STM32F746xx) || \
138 defined(CPU_LINE_STM32F750xx) || \
139 defined(CPU_LINE_STM32F756xx) || \
140 defined(CPU_LINE_STM32F765xx) || \
141 defined(CPU_LINE_STM32F767xx) || \
142 defined(CPU_LINE_STM32F769xx) || \
143 defined(CPU_LINE_STM32F777xx) || \
144 defined(CPU_LINE_STM32F779xx)
145#define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
146#elif defined(CPU_LINE_STM32F722xx) || \
147 defined(CPU_LINE_STM32F723xx) || \
148 defined(CPU_LINE_STM32F730xx) || \
149 defined(CPU_LINE_STM32F732xx) || \
150 defined(CPU_LINE_STM32F733xx)
151#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
152#else
153/* Intentionally error on an unknown line to prevent flashpage errors */
154#error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
155#endif
156
157#else /* CPU_FAM_STM32F7 */
158#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
159#endif
160
161#if FLASHPAGE_DUAL_BANK
162/* Number of "large" sectors + 4 for the small sectors that together equal a
163 * single large sector. Times two to account for the two banks */
164#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
165 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
166#else
167/* Number of "large" sectors + 4 for the small sectors that together equal a
168 * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
169 * sectors */
170#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
171 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
172#endif
173
174#endif
175
176/* The minimum block size which can be written depends on the family.
177 * However, the erase block is always FLASHPAGE_SIZE.
178 */
179#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
180 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
181 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
182 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
183#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
184typedef uint64_t stm32_flashpage_block_t;
185#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
186 defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
187 defined(CPU_FAM_STM32F7)
188#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
189typedef uint32_t stm32_flashpage_block_t;
190#else
191#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
192typedef uint16_t stm32_flashpage_block_t;
193#endif
194
195#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
196 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
197 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
198 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
199#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
200#else
201/* Writing should be always 4 bytes aligned */
202#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
203#endif
205
210#ifdef SRAM_BB_BASE
211#define CPU_HAS_BITBAND 1
212#endif
214
215#ifdef __cplusplus
216}
217#endif
218