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cpu_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2016 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21#include "cpu_conf_common.h"
22
23#if defined(CPU_LINE_STM32F030x4)
24#include "vendor/stm32f030x4.h"
25#elif defined(CPU_LINE_STM32MP157Cxx)
26#include "vendor/stm32mp157cxx_cm4.h"
27#elif CPU_FAM_STM32F0
28#include "stm32f0xx.h"
29#include "irqs/f0/irqs.h"
30#elif CPU_FAM_STM32F1
31#include "stm32f1xx.h"
32#include "irqs/f1/irqs.h"
33#elif CPU_FAM_STM32F2
34#include "stm32f2xx.h"
35#include "irqs/f2/irqs.h"
36#elif CPU_FAM_STM32F3
37#include "stm32f3xx.h"
38#include "irqs/f3/irqs.h"
39#elif CPU_FAM_STM32F4
40#include "stm32f4xx.h"
41#include "irqs/f4/irqs.h"
42#elif CPU_FAM_STM32F7
43#include "stm32f7xx.h"
44#include "irqs/f7/irqs.h"
45#elif CPU_FAM_STM32G0
46#include "stm32g0xx.h"
47#include "irqs/g0/irqs.h"
48#elif CPU_FAM_STM32C0
49#include "stm32c0xx.h"
50#include "irqs/c0/irqs.h"
51#elif CPU_FAM_STM32G4
52#include "stm32g4xx.h"
53#include "irqs/g4/irqs.h"
54#elif CPU_FAM_STM32L0
55#include "stm32l0xx.h"
56#include "irqs/l0/irqs.h"
57#elif CPU_FAM_STM32L1
58#include "stm32l1xx.h"
59#include "irqs/l1/irqs.h"
60#elif CPU_FAM_STM32L4
61#include "stm32l4xx.h"
62#include "irqs/l4/irqs.h"
63#elif CPU_FAM_STM32L5
64#include "stm32l5xx.h"
65#include "irqs/l5/irqs.h"
66#elif CPU_FAM_STM32U5
67#include "stm32u5xx.h"
68#include "irqs/u5/irqs.h"
69#define NUM_HEAPS 3
70#elif CPU_FAM_STM32WB
71#include "stm32wbxx.h"
72#include "irqs/wb/irqs.h"
73#elif CPU_FAM_STM32WL
74#include "stm32wlxx.h"
75#include "irqs/wl/irqs.h"
76#else
77#error Not supported CPU family
78#endif
79
80/* add unused backup RAM as extra heap */
81#if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
82#define NUM_HEAPS 2
83#endif
84
85#ifdef __cplusplus
86extern "C" {
87#endif
88
97#define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
98
103#define CPU_DEFAULT_IRQ_PRIO (1U)
104/* STM32MP1 family has no flah */
105#if !defined(CPU_FAM_STM32MP1)
106#define CPU_FLASH_BASE FLASH_BASE
107#endif
108
109/* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
110#if defined(CPU_LINE_STM32F030x4)
111#define CPU_IRQ_NUMOF (28U)
112#elif defined(CPU_MODEL_STM32MP157CAC)
113#define CPU_IRQ_NUMOF (150U)
114#endif
116
121#if defined(CPU_FAM_STM32U5)
122#define FLASHPAGE_SIZE (8192U)
123#elif defined(CPU_FAM_STM32WB)
124#define FLASHPAGE_SIZE (4096U)
125#elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
126 || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
127 || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
128 || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
129 || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
130 || defined(CPU_FAM_STM32C0)
131#define FLASHPAGE_SIZE (2048U)
132#elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
133 || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
134 || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
135 || defined(CPU_LINE_STM32F031x6)
136#define FLASHPAGE_SIZE (1024U)
137#elif defined(CPU_FAM_STM32L1)
138#define FLASHPAGE_SIZE (256U)
139#elif defined(CPU_FAM_STM32L0)
140#define FLASHPAGE_SIZE (128U)
141#endif
142
143#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
144#define FLASHPAGE_ERASE_STATE (0x00U)
145#endif
146
147#ifdef FLASHPAGE_SIZE
148#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
149#endif
150
151#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
152 defined(CPU_FAM_STM32F7)
153#define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
154#define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
155
167#if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
168#define FLASHPAGE_DUAL_BANK 1
169#else
170#define FLASHPAGE_DUAL_BANK 0
171#endif
172
173/* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
174#if defined(CPU_FAM_STM32F7)
175#if defined(CPU_LINE_STM32F745xx) || \
176 defined(CPU_LINE_STM32F746xx) || \
177 defined(CPU_LINE_STM32F750xx) || \
178 defined(CPU_LINE_STM32F756xx) || \
179 defined(CPU_LINE_STM32F765xx) || \
180 defined(CPU_LINE_STM32F767xx) || \
181 defined(CPU_LINE_STM32F769xx) || \
182 defined(CPU_LINE_STM32F777xx) || \
183 defined(CPU_LINE_STM32F779xx)
184#define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
185#elif defined(CPU_LINE_STM32F722xx) || \
186 defined(CPU_LINE_STM32F723xx) || \
187 defined(CPU_LINE_STM32F730xx) || \
188 defined(CPU_LINE_STM32F732xx) || \
189 defined(CPU_LINE_STM32F733xx)
190#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
191#else
192/* Intentionally error on an unknown line to prevent flashpage errors */
193#error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
194#endif
195
196#else /* CPU_FAM_STM32F7 */
197#define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
198#endif
199
200#if FLASHPAGE_DUAL_BANK
201/* Number of "large" sectors + 4 for the small sectors that together equal a
202 * single large sector. Times two to account for the two banks */
203#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
204 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
205#else
206/* Number of "large" sectors + 4 for the small sectors that together equal a
207 * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
208 * sectors */
209#define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
210 (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
211#endif
212
213#endif
214
215/* The minimum block size which can be written depends on the family.
216 * However, the erase block is always FLASHPAGE_SIZE.
217 */
218#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
219 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
220 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
221 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
222#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
223typedef uint64_t stm32_flashpage_block_t;
224#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
225 defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
226 defined(CPU_FAM_STM32F7)
227#define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
228typedef uint32_t stm32_flashpage_block_t;
229#else
230#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
231typedef uint16_t stm32_flashpage_block_t;
232#endif
233
234#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
235 defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
236 defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
237 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
238#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
239#else
240/* Writing should be always 4 bytes aligned */
241#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
242#endif
244
249#ifdef SRAM_BB_BASE
250#define CPU_HAS_BITBAND 1
251#endif
253
254#ifdef __cplusplus
255}
256#endif
257