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cpu_common.h
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1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21
22#include "cpu_conf.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#ifdef Doxygen
33#define STM32_BOOTLOADER_ADDR
34#endif
35
41#define CPUID_LEN (12U)
42
46#ifndef CPUID_ADDR
47#define CPUID_ADDR (UID_BASE)
48#endif
49
53#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
54 defined(CPU_FAM_STM32F3)
55#define CLOCK_LSI (40000U)
56#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
57#define CLOCK_LSI (37000U)
58#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
59 defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
60 defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
61 defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
62 defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
63 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0) || \
64 defined(CPU_FAM_STM32H7)
65#define CLOCK_LSI (32000U)
66#else
67#error "error: LSI clock speed not defined for your target CPU"
68#endif
69
70/* if CPU has APB1 bus */
71#if defined(CPU_FAM_STM32G4) || \
72 defined(CPU_FAM_STM32L4) || \
73 defined(CPU_FAM_STM32L5) || \
74 defined(CPU_FAM_STM32U5) || \
75 defined(CPU_FAM_STM32WB) || \
76 defined(CPU_FAM_STM32WL)
77 #define APB1_PERIPH_EN RCC->APB1ENR1
78 #define APB12_PERIPH_EN RCC->APB1ENR2
79#elif defined(CPU_FAM_STM32C0) || \
80 defined(CPU_FAM_STM32G0)
81 #define APB1_PERIPH_EN RCC->APBENR1
82 #define APB12_PERIPH_EN RCC->APBENR2
83#elif defined(CPU_FAM_STM32H7)
84 #define APB1_PERIPH_EN RCC->APB1LENR
85 #define APB12_PERIPH_EN RCC->APB1HENR
86#elif defined(CPU_FAM_STM32MP1)
87 #define APB1_PERIPH_EN RCC->MC_APB1ENSETR
88 #define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
89#elif defined(APB1PERIPH_BASE) || \
90 defined(CPU_FAM_STM32F0) || \
91 defined(CPU_FAM_STM32L0)
92 #define APB1_PERIPH_EN RCC->APB1ENR
93#endif
94
95/* if CPU has APB2 bus */
96#if defined(CPU_FAM_STM32MP1)
97 #define APB2_PERIPH_EN RCC->MC_APB2ENSETR
98 #define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
99#elif defined(APB2PERIPH_BASE) || \
100 defined(CPU_FAM_STM32F0) || \
101 defined(CPU_FAM_STM32L0) || \
102 defined(CPU_FAM_STM32H7)
103 #define APB2_PERIPH_EN RCC->APB2ENR
104#endif
105
106/* if CPU has APB3 bus */
107#if defined(CPU_FAM_STM32WB)
108 /* CPU has APB3, but no periph enable registers for the bus. */
109 #undef APB3_PERIPH_EN /* not defined */
110#elif defined(APB3PERIPH_BASE) || \
111 defined(APB3PERIPH_BASE_S) || \
112 defined(CPU_FAM_STM32H7)
113 #define APB3_PERIPH_EN RCC->APB3ENR
114#endif
115
116/* if CPU has APB4 bus */
117#if defined(CPU_FAM_STM32H7)
118 #define APB4_PERIPH_EN RCC->APB4ENR
119#endif
120
121/* if CPU has AHB/AHB1 bus */
122#if defined(AHBPERIPH_BASE) || \
123 defined(CPU_FAM_STM32F3)
124 #define AHB_PERIPH_EN RCC->AHBENR
125#elif defined(CPU_FAM_STM32MP1)
126 /* CPU has AHB1, but no periph enable registers for the bus. */
127 #undef AHB1_PERIPH_EN /* not defined */
128 #undef AHB1_PERIPH_DIS /* not defined */
129#elif defined(AHB1PERIPH_BASE) || \
130 defined(CPU_FAM_STM32H7)
131 #define AHB1_PERIPH_EN RCC->AHB1ENR
132#endif
133
134/* if CPU has AHB2 bus */
135#if defined(CPU_FAM_STM32F0) || \
136 defined(CPU_FAM_STM32F3)
137 /* CPU has AHB2, but no periph enable registers for the bus. */
138 #undef AHB2_PERIPH_EN /* not defined */
139#elif defined(CPU_FAM_STM32U5)
140 #define AHB2_PERIPH_EN RCC->AHB2ENR1
141 #define AHB22_PERIPH_EN RCC->AHB2ENR2
142#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
143 #define AHB2_PERIPH_EN RCC->AHB2ENR
144#elif defined(CPU_FAM_STM32MP1)
145 #define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
146 #define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
147#elif defined(AHB2PERIPH_BASE) || \
148 defined(CPU_FAM_STM32H7)
149 #define AHB2_PERIPH_EN RCC->AHB2ENR
150#endif
151
152/* if CPU has AHB3 bus */
153#if defined(CPU_FAM_STM32F3)
154 /* CPU has AHB3, but no periph enable registers for the bus. */
155 #undef AHB3_PERIPH_EN /* not defined */
156#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
157 #define AHB3_PERIPH_EN RCC->AHB3ENR
158#elif defined(CPU_FAM_STM32MP1)
159 #define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
160 #define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
161#elif defined(AHB3PERIPH_BASE) || \
162 defined(AHB3PERIPH_BASE_S) || \
163 defined(CPU_FAM_STM32F2) || \
164 defined(CPU_FAM_STM32F7) || \
165 defined(CPU_FAM_STM32G4) || \
166 defined(CPU_FAM_STM32L4) || \
167 defined(CPU_FAM_STM32H7)
168 #define AHB3_PERIPH_EN RCC->AHB3ENR
169#endif
170
171/* if CPU has AHB4 bus */
172#if defined(CPU_FAM_STM32MP1)
173 #define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
174 #define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
175#elif defined(CPU_FAM_STM32H7)
176 #define AHB4_PERIPH_EN RCC->AHB4ENR
177#elif defined(AHB4PERIPH_BASE)
178 /* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
179 #define AHB4_PERIPH_EN RCC->AHB3ENR
180#endif
181
182/* if CPU has IOP bus */
183#if defined(IOPPERIPH_BASE) || \
184 defined(RCC_IOPENR_GPIOAEN) || \
185 defined(RCC_IOPENR_IOPAEN)
186 #define IOP_PERIPH_EN RCC->IOPENR
187#endif
188
192typedef enum {
193#if defined(APB1_PERIPH_EN)
194 APB1,
195#endif
196#if defined(APB12_PERIPH_EN)
197 APB12,
198#endif
199#if defined(APB2_PERIPH_EN)
200 APB2,
201#endif
202#if defined(APB3_PERIPH_EN)
203 APB3,
204#endif
205#if defined(APB4_PERIPH_EN)
206 APB4,
207#endif
208#if defined(AHB_PERIPH_EN)
209 AHB,
210#endif
211#if defined(AHB1_PERIPH_EN)
212 AHB1,
213#endif
214#if defined(AHB2_PERIPH_EN)
215 AHB2,
216#endif
217#if defined(AHB22_PERIPH_EN)
218 AHB22,
219#endif
220#if defined(AHB3_PERIPH_EN)
221 AHB3,
222#endif
223#if defined(AHB4_PERIPH_EN)
224 AHB4,
225#endif
226#if defined(IOP_PERIPH_EN)
227 IOP,
228#endif
229 BUS_NUMOF
230} bus_t;
231
239uint32_t periph_apb_clk(bus_t bus);
240
248uint32_t periph_timer_clk(bus_t bus);
249
256void periph_clk_en(bus_t bus, uint32_t mask);
257
264void periph_clk_dis(bus_t bus, uint32_t mask);
265
272void periph_lpclk_en(bus_t bus, uint32_t mask);
273
280void periph_lpclk_dis(bus_t bus, uint32_t mask);
281
282#ifdef __cplusplus
283}
284#endif
285
bus_t
bus_t
On-Chip buses.
Definition periph_cpu.h:73
APB1
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
AHB
@ AHB
Advanced High-performance Bus.
Definition periph_cpu.h:74
APB2
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
periph_apb_clk
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
periph_timer_clk
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
BUS_NUMOF
@ BUS_NUMOF
number of buses
Definition cpu_common.h:229