Loading...
Searching...
No Matches
cpu_common.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21
22#include "cpu_conf.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#ifdef Doxygen
33#define STM32_BOOTLOADER_ADDR
34#endif
35
41#define CPUID_LEN (12U)
42
46#ifndef CPUID_ADDR
47#define CPUID_ADDR (UID_BASE)
48#endif
49
53#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
54 defined(CPU_FAM_STM32F3)
55#define CLOCK_LSI (40000U)
56#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
57#define CLOCK_LSI (37000U)
58#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
59 defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
60 defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
61 defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
62 defined(CPU_FAM_STM32U3) || defined(CPU_FAM_STM32MP1) || \
63 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0) || \
64 defined(CPU_FAM_STM32H7) || defined(CPU_FAM_STM32U5)
65#define CLOCK_LSI (32000U)
66#else
67#error "error: LSI clock speed not defined for your target CPU"
68#endif
69
70/* if CPU has APB1 bus */
71#if defined(CPU_FAM_STM32G4) || \
72 defined(CPU_FAM_STM32L4) || \
73 defined(CPU_FAM_STM32L5) || \
74 defined(CPU_FAM_STM32U3) || \
75 defined(CPU_FAM_STM32U5) || \
76 defined(CPU_FAM_STM32WB) || \
77 defined(CPU_FAM_STM32WL)
78 #define APB1_PERIPH_EN RCC->APB1ENR1
79 #define APB12_PERIPH_EN RCC->APB1ENR2
80#elif defined(CPU_FAM_STM32C0) || \
81 defined(CPU_FAM_STM32G0)
82 #define APB1_PERIPH_EN RCC->APBENR1
83 #define APB12_PERIPH_EN RCC->APBENR2
84#elif defined(CPU_FAM_STM32H7)
85 #define APB1_PERIPH_EN RCC->APB1LENR
86 #define APB12_PERIPH_EN RCC->APB1HENR
87#elif defined(CPU_FAM_STM32MP1)
88 #define APB1_PERIPH_EN RCC->MC_APB1ENSETR
89 #define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
90#elif defined(APB1PERIPH_BASE) || \
91 defined(CPU_FAM_STM32F0) || \
92 defined(CPU_FAM_STM32L0)
93 #define APB1_PERIPH_EN RCC->APB1ENR
94#endif
95
96/* if CPU has APB2 bus */
97#if defined(CPU_FAM_STM32MP1)
98 #define APB2_PERIPH_EN RCC->MC_APB2ENSETR
99 #define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
100#elif defined(APB2PERIPH_BASE) || \
101 defined(CPU_FAM_STM32F0) || \
102 defined(CPU_FAM_STM32L0) || \
103 defined(CPU_FAM_STM32H7) || \
104 defined(CPU_FAM_STM32U3)
105 #define APB2_PERIPH_EN RCC->APB2ENR
106#endif
107
108/* if CPU has APB3 bus */
109#if defined(CPU_FAM_STM32WB)
110 /* CPU has APB3, but no periph enable registers for the bus. */
111 #undef APB3_PERIPH_EN /* not defined */
112#elif defined(APB3PERIPH_BASE) || \
113 defined(APB3PERIPH_BASE_NS) || \
114 defined(APB3PERIPH_BASE_S) || \
115 defined(CPU_FAM_STM32H7) || \
116 defined(CPU_FAM_STM32U3)
117 #define APB3_PERIPH_EN RCC->APB3ENR
118#endif
119
120/* if CPU has APB4 bus */
121#if defined(CPU_FAM_STM32H7)
122 #define APB4_PERIPH_EN RCC->APB4ENR
123#endif
124
125/* if CPU has AHB/AHB1 bus */
126#if defined(AHBPERIPH_BASE) || \
127 defined(CPU_FAM_STM32F3)
128 #define AHB_PERIPH_EN RCC->AHBENR
129#elif defined(CPU_FAM_STM32U3)
130 #define AHB1_PERIPH_EN RCC->AHB1ENR1
131 #define AHB12_PERIPH_EN RCC->AHB1ENR2
132#elif defined(CPU_FAM_STM32MP1)
133 /* CPU has AHB1, but no periph enable registers for the bus. */
134 #undef AHB1_PERIPH_EN /* not defined */
135 #undef AHB1_PERIPH_DIS /* not defined */
136#elif defined(AHB1PERIPH_BASE) || \
137 defined(CPU_FAM_STM32H7)
138 #define AHB1_PERIPH_EN RCC->AHB1ENR
139#endif
140
141/* if CPU has AHB2 bus */
142#if defined(CPU_FAM_STM32F0) || \
143 defined(CPU_FAM_STM32F3)
144 /* CPU has AHB2, but no periph enable registers for the bus. */
145 #undef AHB2_PERIPH_EN /* not defined */
146#elif defined(CPU_FAM_STM32U3) || \
147 defined(CPU_FAM_STM32U5)
148 #define AHB2_PERIPH_EN RCC->AHB2ENR1
149 #define AHB22_PERIPH_EN RCC->AHB2ENR2
150#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
151 #define AHB2_PERIPH_EN RCC->AHB2ENR
152#elif defined(CPU_FAM_STM32MP1)
153 #define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
154 #define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
155#elif defined(AHB2PERIPH_BASE) || \
156 defined(CPU_FAM_STM32H7)
157 #define AHB2_PERIPH_EN RCC->AHB2ENR
158#endif
159
160/* if CPU has AHB3 bus */
161#if defined(CPU_FAM_STM32F3)
162 /* CPU has AHB3, but no periph enable registers for the bus. */
163 #undef AHB3_PERIPH_EN /* not defined */
164#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
165 #define AHB3_PERIPH_EN RCC->AHB3ENR
166#elif defined(CPU_FAM_STM32MP1)
167 #define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
168 #define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
169#elif defined(AHB3PERIPH_BASE) || \
170 defined(AHB3PERIPH_BASE_S) || \
171 defined(CPU_FAM_STM32F2) || \
172 defined(CPU_FAM_STM32F7) || \
173 defined(CPU_FAM_STM32G4) || \
174 defined(CPU_FAM_STM32L4) || \
175 defined(CPU_FAM_STM32H7)
176 #define AHB3_PERIPH_EN RCC->AHB3ENR
177#endif
178
179/* if CPU has AHB4 bus */
180#if defined(CPU_FAM_STM32MP1)
181 #define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
182 #define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
183#elif defined(CPU_FAM_STM32H7)
184 #define AHB4_PERIPH_EN RCC->AHB4ENR
185#elif defined(AHB4PERIPH_BASE)
186 /* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
187 #define AHB4_PERIPH_EN RCC->AHB3ENR
188#endif
189
190/* if CPU has IOP bus */
191#if defined(IOPPERIPH_BASE) || \
192 defined(RCC_IOPENR_GPIOAEN) || \
193 defined(RCC_IOPENR_IOPAEN)
194 #define IOP_PERIPH_EN RCC->IOPENR
195#endif
196
200typedef enum {
201#if defined(APB1_PERIPH_EN)
202 APB1,
203#endif
204#if defined(APB12_PERIPH_EN)
205 APB12,
206#endif
207#if defined(APB2_PERIPH_EN)
208 APB2,
209#endif
210#if defined(APB3_PERIPH_EN)
211 APB3,
212#endif
213#if defined(APB4_PERIPH_EN)
214 APB4,
215#endif
216#if defined(AHB_PERIPH_EN)
217 AHB,
218#endif
219#if defined(AHB1_PERIPH_EN)
220 AHB1,
221#endif
222#if defined(AHB12_PERIPH_EN)
223 AHB12,
224#endif
225#if defined(AHB2_PERIPH_EN)
226 AHB2,
227#endif
228#if defined(AHB22_PERIPH_EN)
229 AHB22,
230#endif
231#if defined(AHB3_PERIPH_EN)
232 AHB3,
233#endif
234#if defined(AHB4_PERIPH_EN)
235 AHB4,
236#endif
237#if defined(IOP_PERIPH_EN)
238 IOP,
239#endif
240 BUS_NUMOF
241} bus_t;
242
250uint32_t periph_apb_clk(bus_t bus);
251
259uint32_t periph_timer_clk(bus_t bus);
260
267void periph_clk_en(bus_t bus, uint32_t mask);
268
275void periph_clk_dis(bus_t bus, uint32_t mask);
276
283void periph_lpclk_en(bus_t bus, uint32_t mask);
284
291void periph_lpclk_dis(bus_t bus, uint32_t mask);
292
293#ifdef __cplusplus
294}
295#endif
296
bus_t
bus_t
On-Chip buses.
Definition periph_cpu.h:73
APB1
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
AHB
@ AHB
Advanced High-performance Bus.
Definition periph_cpu.h:74
APB2
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
periph_apb_clk
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
periph_timer_clk
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
BUS_NUMOF
@ BUS_NUMOF
number of buses
Definition cpu_common.h:240