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periph_conf.h
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1/*
2 * Copyright (C) 2015 Eistec AB
3 * 2016 Freie Universität Berlin
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser General
6 * Public License v2.1. See the file LICENSE in the top level directory for more
7 * details.
8 */
9
21#ifndef PERIPH_CONF_H
22#define PERIPH_CONF_H
23
24#include "periph_cpu.h"
25
26#ifdef __cplusplus
27extern "C"
28{
29#endif
30
35/* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
36 * to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
37 * XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
38 * capacitance as well. */
39/* Use the equation
40 * CL = (C1 * C2) / (C1 + C2) + Cstray
41 * with C1 == C2:
42 * C1 = 2 * (CL - Cstray)
43 */
44/* enable 14pF load capacitor which will yield a crystal load capacitance of 12 pF */
45#define RTC_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK)
46
47static const clock_config_t clock_config = {
48 /*
49 * This configuration results in the system running from the FLL output with
50 * the following clock frequencies:
51 * Core: 48 MHz
52 * Bus: 48 MHz
53 * Flex: 24 MHz
54 * Flash: 24 MHz
55 */
56 /* The board has a 16 MHz crystal, though it is not used in this configuration */
57 /* This configuration uses the RTC crystal to provide the base clock, it
58 * should have better accuracy than the internal slow clock, and lower power
59 * consumption than using the 16 MHz crystal and the OSC0 module */
60 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) |
61 SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(1),
62 .rtc_clc = RTC_LOAD_CAP_BITS,
63 .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
64 .clock_flags =
65 /* no OSC0_EN, the RTC module provides the clock input signal for the FLL */
66 KINETIS_CLOCK_RTCOSC_EN |
67 KINETIS_CLOCK_USE_FAST_IRC |
68 0,
69 .default_mode = KINETIS_MCG_MODE_FEE,
70 .erc_range = KINETIS_MCG_ERC_RANGE_LOW, /* Input clock is 32768 Hz */
71 /* 16 pF capacitors yield ca 10 pF load capacitance as required by the
72 * onboard xtal, not used when OSC0 is disabled */
73 .osc_clc = OSC_CR_SC16P_MASK,
74 .oscsel = MCG_C7_OSCSEL(1), /* Use RTC for external clock */
75 .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
76 .fll_frdiv = MCG_C1_FRDIV(0b000), /* Divide by 1 => FLL input 32768 Hz */
77 .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
78 .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
79 /* PLL is unavailable when using a 32768 Hz source clock, so the
80 * configuration below can only be used if the above config is modified to
81 * use the 16 MHz crystal instead of the RTC. */
82 .pll_prdiv = MCG_C5_PRDIV0(0b00111), /* Divide by 8 */
83 .pll_vdiv = MCG_C6_VDIV0(0b01100), /* Multiply by 36 => PLL freq = 72 MHz */
84};
85#define CLOCK_CORECLOCK (48000000ul)
86#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
93#define PIT_NUMOF (2U)
94#define PIT_CONFIG { \
95 { \
96 .prescaler_ch = 0, \
97 .count_ch = 1, \
98 }, \
99 { \
100 .prescaler_ch = 2, \
101 .count_ch = 3, \
102 }, \
103 }
104#define LPTMR_NUMOF (1U)
105#define LPTMR_CONFIG { \
106 { \
107 .dev = LPTMR0, \
108 .irqn = LPTMR0_IRQn, \
109 .src = 2, \
110 .base_freq = 32768u, \
111 } \
112 }
113#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
114
115#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
116#define PIT_ISR_0 isr_pit1
117#define PIT_ISR_1 isr_pit3
118#define LPTMR_ISR_0 isr_lptmr0
119
126static const uart_conf_t uart_config[] = {
127 {
128 .dev = UART0,
129 .freq = CLOCK_CORECLOCK,
130 .pin_rx = GPIO_PIN(PORT_A, 15),
131 .pin_tx = GPIO_PIN(PORT_A, 14),
132 .pcr_rx = PORT_PCR_MUX(3),
133 .pcr_tx = PORT_PCR_MUX(3),
134 .irqn = UART0_RX_TX_IRQn,
135 .scgc_addr = &SIM->SCGC4,
136 .scgc_bit = SIM_SCGC4_UART0_SHIFT,
137 .mode = UART_MODE_8N1,
138 .type = KINETIS_UART,
139 },
140 {
141 .dev = UART1,
142 .freq = CLOCK_CORECLOCK,
143 .pin_rx = GPIO_PIN(PORT_C, 3),
144 .pin_tx = GPIO_PIN(PORT_C, 4),
145 .pcr_rx = PORT_PCR_MUX(3),
146 .pcr_tx = PORT_PCR_MUX(3),
147 .irqn = UART1_RX_TX_IRQn,
148 .scgc_addr = &SIM->SCGC4,
149 .scgc_bit = SIM_SCGC4_UART1_SHIFT,
150 .mode = UART_MODE_8N1,
151 .type = KINETIS_UART,
152 },
153};
154
155#define UART_0_ISR (isr_uart0_rx_tx)
156#define UART_1_ISR (isr_uart1_rx_tx)
157
158#define UART_NUMOF ARRAY_SIZE(uart_config)
165static const adc_conf_t adc_config[] = {
166 /* internal: temperature sensor */
167 /* The temperature sensor has a very high output impedance, it must not be
168 * sampled using hardware averaging, or the sampled values will be garbage */
169 [ 0] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 26, .avg = ADC_AVG_NONE },
170 /* internal: band gap */
171 [ 1] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 27, .avg = ADC_AVG_MAX },
172 /* internal: V_REFSH */
173 [ 2] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 29, .avg = ADC_AVG_MAX },
174 /* internal: V_REFSL */
175 [ 3] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 30, .avg = ADC_AVG_MAX },
176 /* internal: DAC0 module output level */
177 [ 4] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 23, .avg = ADC_AVG_MAX },
178 /* internal: VREF module output level */
179 [ 5] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 18, .avg = ADC_AVG_MAX },
180 /* on board connection to Mulle Vbat/2 on PGA1_DP pin */
181 [ 6] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 0, .avg = ADC_AVG_MAX },
182 /* on board connection to Mulle Vchr/2 on PGA1_DM pin */
183 [ 7] = { .dev = ADC1, .pin = GPIO_UNDEF, .chan = 19, .avg = ADC_AVG_MAX },
184 /* expansion port PGA0_DP pin */
185 [ 8] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 0, .avg = ADC_AVG_MAX },
186 /* expansion port PGA0_DM pin */
187 [ 9] = { .dev = ADC0, .pin = GPIO_UNDEF, .chan = 19, .avg = ADC_AVG_MAX },
188 /* expansion port PTA17 */
189 [10] = { .dev = ADC1, .pin = GPIO_PIN(PORT_A, 17), .chan = 17, .avg = ADC_AVG_MAX },
190 /* expansion port PTB0 */
191 [11] = { .dev = ADC1, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX },
192 /* expansion port PTC0 */
193 [12] = { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 0), .chan = 14, .avg = ADC_AVG_MAX },
194 /* expansion port PTC8 */
195 [13] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 8), .chan = 4, .avg = ADC_AVG_MAX },
196 /* expansion port PTC9 */
197 [14] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 9), .chan = 5, .avg = ADC_AVG_MAX },
198 /* expansion port PTC10 */
199 [15] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 10), .chan = 6, .avg = ADC_AVG_MAX },
200 /* expansion port PTC11 */
201 [16] = { .dev = ADC1, .pin = GPIO_PIN(PORT_C, 11), .chan = 7, .avg = ADC_AVG_MAX },
202};
203
204#define ADC_NUMOF ARRAY_SIZE(adc_config)
205/*
206 * K60D ADC reference settings:
207 * 0: VREFH/VREFL external pin pair
208 * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
209 * 2-3: reserved
210 */
211#define ADC_REF_SETTING 0
218static const dac_conf_t dac_config[] = {
219 {
220 .dev = DAC0,
221 .scgc_addr = &SIM->SCGC2,
222 .scgc_bit = SIM_SCGC2_DAC0_SHIFT
223 }
224};
225
226#define DAC_NUMOF ARRAY_SIZE(dac_config)
233static const pwm_conf_t pwm_config[] = {
234 {
235 .ftm = FTM0,
236 .chan = {
237 { .pin = GPIO_PIN(PORT_C, 1), .af = 4, .ftm_chan = 0 },
238 { .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
239 { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
240 { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
241 },
242 .chan_numof = 2,
243 .ftm_num = 0
244 },
245 {
246 .ftm = FTM1,
247 .chan = {
248 { .pin = GPIO_PIN(PORT_A, 12), .af = 3, .ftm_chan = 0 },
249 { .pin = GPIO_PIN(PORT_A, 13), .af = 3, .ftm_chan = 1 },
250 { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 },
251 { .pin = GPIO_UNDEF, .af = 0, .ftm_chan = 0 }
252 },
253 .chan_numof = 2,
254 .ftm_num = 1
255 }
256};
257
258#define PWM_NUMOF ARRAY_SIZE(pwm_config)
271static const uint32_t spi_clk_config[] = {
272 (
273 SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93728Hz */
274 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
275 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
276 SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
277 ),
278 (
279 SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 374912Hz */
280 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
281 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
282 SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
283 ),
284 (
285 SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 999765Hz */
286 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
287 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
288 SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
289 ),
290 (
291 SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4798873Hz */
292 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
293 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
294 SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
295 ),
296 (
297 SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 7998122Hz */
298 SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
299 SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
300 SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
301 )
302};
303
304static const spi_conf_t spi_config[] = {
305 {
306 .dev = SPI0,
307 .pin_miso = GPIO_PIN(PORT_D, 3),
308 .pin_mosi = GPIO_PIN(PORT_D, 2),
309 .pin_clk = GPIO_PIN(PORT_D, 1),
310 .pin_cs = {
311 GPIO_PIN(PORT_D, 0),
312 GPIO_PIN(PORT_D, 4),
313 GPIO_PIN(PORT_D, 5),
314 GPIO_PIN(PORT_D, 6),
316 },
317 .pcr = GPIO_AF_2,
318 .simmask = SIM_SCGC6_SPI0_MASK
319 },
320 {
321 .dev = SPI1,
322 .pin_miso = GPIO_PIN(PORT_E, 3),
323 .pin_mosi = GPIO_PIN(PORT_E, 1),
324 .pin_clk = GPIO_PIN(PORT_E, 2),
325 .pin_cs = {
326 GPIO_PIN(PORT_E, 4),
331 },
332 .pcr = GPIO_AF_2,
333 .simmask = SIM_SCGC6_SPI1_MASK
334 }
335};
336
337#define SPI_NUMOF ARRAY_SIZE(spi_config)
344static const i2c_conf_t i2c_config[] = {
345 {
346 .i2c = I2C0,
347 .scl_pin = GPIO_PIN(PORT_B, 2),
348 .sda_pin = GPIO_PIN(PORT_B, 1),
349 .freq = CLOCK_BUSCLOCK,
350 .speed = I2C_SPEED_FAST,
351 .irqn = I2C0_IRQn,
352 .scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
353 .sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
354 },
355};
356#define I2C_NUMOF ARRAY_SIZE(i2c_config)
357#define I2C_0_ISR (isr_i2c0)
358#define I2C_1_ISR (isr_i2c1)
361#ifdef __cplusplus
362}
363#endif
364
365#endif /* PERIPH_CONF_H */
#define CLOCK_CORECLOCK
Clock configuration.
Definition periph_cpu.h:31
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:279
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
#define UART0
UART0 register bank.
#define UART1
UART1 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition mcg.h:147
#define ADC_AVG_NONE
Disable hardware averaging.
Definition periph_cpu.h:370
@ KINETIS_UART
Kinetis UART module type.
Definition periph_cpu.h:538
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:294
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition periph_cpu.h:374
ADC device configuration.
Definition periph_cpu.h:379
ADC_TypeDef * dev
ADC device used.
Definition periph_cpu.h:380
DAC line configuration data.
Definition periph_cpu.h:301
I2C configuration structure.
Definition periph_cpu.h:299
I2C_Type * i2c
Pointer to hardware module registers.
Definition periph_cpu.h:459
gpio_t pin
GPIO pin mapped to this channel.
Definition periph_cpu.h:470
PWM device configuration.
pwm_chan_t chan[TIMER_CHANNEL_NUMOF]
channel mapping set to {GPIO_UNDEF, 0} if not used
Definition periph_cpu.h:483
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219