23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
33#ifndef CONFIG_CLOCK_HSE
34#define CONFIG_CLOCK_HSE MHZ(25)
39#include "periph_cpu.h"
41#include "cfg_rtt_default.h"
43#if defined(MODULE_PERIPH_USBDEV_HS_ULPI)
69#define DMA_0_ISR isr_dma2_stream7
70#define DMA_1_ISR isr_dma2_stream6
71#define DMA_2_ISR isr_dma1_stream6
73#define DMA_3_ISR isr_dma2_stream2
74#define DMA_4_ISR isr_dma2_stream5
75#define DMA_5_ISR isr_dma2_stream3
76#define DMA_6_ISR isr_dma2_stream4
78#define DMA_7_ISR isr_dma2_stream0
80#define DMA_NUMOF ARRAY_SIZE(dma_config)
90 .rcc_mask = RCC_APB2ENR_USART1EN,
97#ifdef MODULE_PERIPH_DMA
104 .rcc_mask = RCC_APB2ENR_USART6EN,
111#ifdef MODULE_PERIPH_DMA
118#define UART_0_ISR (isr_usart1)
119#define UART_0_DMA_ISR (isr_dma2_stream7)
120#define UART_6_ISR (isr_usart6)
121#define UART_6_DMA_ISR (isr_dma2_stream6)
123#define UART_NUMOF ARRAY_SIZE(uart_config)
141 .rccmask = RCC_APB1ENR_SPI2EN,
143#ifdef MODULE_PERIPH_DMA
152#define SPI_NUMOF ARRAY_SIZE(spi_config)
168 .rcc_mask = RCC_APB1ENR_I2C1EN,
169 .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
170 .irqn = I2C1_ER_IRQn,
180 .rcc_mask = RCC_APB1ENR_I2C3EN,
181 .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
182 .irqn = I2C3_ER_IRQn,
186#define I2C_0_ISR isr_i2c1_er
187#define I2C_1_ISR isr_i2c3_er
189#define I2C_NUMOF ARRAY_SIZE(i2c_config)
215#define ETH_DMA_ISR isr_dma2_stream0
225 .rcc_mask = RCC_APB2ENR_LTDCEN,
275#if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
288#define DWC2_USB_OTG_HS_ENABLED
295 .
periph = USB_OTG_HS_PERIPH_BASE,
298 .rcc_mask = RCC_AHB1ENR_OTGHSEN,
320#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
334 .rcc_mask = RCC_AHB3ENR_FMCEN,
335#if MODULE_PERIPH_FMC_SDRAM
368#if MODULE_PERIPH_FMC_16BIT
400 .address = 0xc0000000,
409 .burst_write =
false,
410 .burst_len = FMC_BURST_LENGTH_1,
411 .burst_interleaved =
false,
412 .write_protect =
false,
415 .row_to_col_delay = 2,
420 .exit_self_refresh = 7,
421 .load_mode_register = 2,
422 .refresh_period = 16,
431#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
446 .rcc_mask = RCC_APB2ENR_SDMMC1EN,
449 .cd_mode = GPIO_IN_PU,
456#ifdef MODULE_PERIPH_DMA
467#define SDMMC_CONFIG_NUMOF 1
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
static const sdmmc_conf_t sdmmc_config[]
SDMMC devices.
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
static const fmc_conf_t fmc_config
FMC controller configuration.
static const ltdc_conf_t ltdc_config
LTDC static configuration struct.
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG HS configuration with ULPI HS PHY.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
@ GPIO_AF5
use alternate function 5
@ GPIO_AF4
use alternate function 4
@ GPIO_AF10
use alternate function 10
@ GPIO_AF9
use alternate function 9
@ GPIO_AF14
use alternate function 14
@ GPIO_AF12
use alternate function 12
@ GPIO_AF7
use alternate function 7
#define SPI_CS_UNDEF
Define value for unused CS line.
@ APB1
Advanced Peripheral Bus 1
@ APB2
Advanced Peripheral Bus 2
@ FMC_SDRAM
SDRAM Controller used.
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
#define MII_BMCR_FULL_DPLX
Set for full duplex.
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Interface definition for MII/RMII h.
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
uintptr_t periph
USB peripheral base address.
Ethernet Peripheral configuration.
eth_mode_t mode
Select configuration mode.
Bank configuration structure.
FMC peripheral configuration.
I2C configuration structure.
TWI_t * dev
Pointer to hardware module registers.
LTDC Peripheral configuration.
SDMMC slot configuration.
gpio_t cd
Card Detect pin (must be GPIO_UNDEF if not connected)
SPI device configuration.
SPI_t * dev
pointer to the used SPI device
UART device configuration.
USART_t * dev
pointer to the used UART device
#define MiB(x)
A macro to return the bytes in x MiB.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_ULPI
ULPI for external HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.