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periph_conf.h
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1/*
2 * Copyright (C) 2021 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32/* The HSE provides a 25MHz clock */
33#ifndef CONFIG_CLOCK_HSE
34#define CONFIG_CLOCK_HSE MHZ(25)
35#endif
36
37#include <stdint.h>
38
39#include "periph_cpu.h"
40#include "clk_conf.h"
41#include "cfg_rtt_default.h"
42#include "cfg_timer_tim2.h"
43#if defined(MODULE_PERIPH_USBDEV_HS_ULPI)
45#else
46#include "cfg_usb_otg_fs.h"
47#endif
48#include "mii.h"
49
50#ifdef __cplusplus
51extern "C" {
52#endif
53
58static const dma_conf_t dma_config[] = {
59 { .stream = 15 }, /* DMA2 Stream 7 - USART1_TX */
60 { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
61 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
62 { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
63 { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
64 { .stream = 11 }, /* DMA2 Stream 3 - SPI4_RX Ch5 / SDMMC1 Ch 4 */
65 { .stream = 12 }, /* DMA2 Stream 4 - SPI4_TX */
66 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
67};
68
69#define DMA_0_ISR isr_dma2_stream7
70#define DMA_1_ISR isr_dma2_stream6
71#define DMA_2_ISR isr_dma1_stream6
72
73#define DMA_3_ISR isr_dma2_stream2
74#define DMA_4_ISR isr_dma2_stream5
75#define DMA_5_ISR isr_dma2_stream3
76#define DMA_6_ISR isr_dma2_stream4
77
78#define DMA_7_ISR isr_dma2_stream0
79
80#define DMA_NUMOF ARRAY_SIZE(dma_config)
87static const uart_conf_t uart_config[] = {
88 {
89 .dev = USART1,
90 .rcc_mask = RCC_APB2ENR_USART1EN,
91 .rx_pin = GPIO_PIN(PORT_B, 7),
92 .tx_pin = GPIO_PIN(PORT_A, 9),
93 .rx_af = GPIO_AF7,
94 .tx_af = GPIO_AF7,
95 .bus = APB2,
96 .irqn = USART1_IRQn,
97#ifdef MODULE_PERIPH_DMA
98 .dma = 0,
99 .dma_chan = 4
100#endif
101 },
102 { /* Arduino connectors */
103 .dev = USART6,
104 .rcc_mask = RCC_APB2ENR_USART6EN,
105 .rx_pin = GPIO_PIN(PORT_C, 6),
106 .tx_pin = GPIO_PIN(PORT_C, 7),
107 .rx_af = GPIO_AF7,
108 .tx_af = GPIO_AF7,
109 .bus = APB2,
110 .irqn = USART6_IRQn,
111#ifdef MODULE_PERIPH_DMA
112 .dma = 1,
113 .dma_chan = 5
114#endif
115 },
116};
117
118#define UART_0_ISR (isr_usart1)
119#define UART_0_DMA_ISR (isr_dma2_stream7)
120#define UART_6_ISR (isr_usart6)
121#define UART_6_DMA_ISR (isr_dma2_stream6)
122
123#define UART_NUMOF ARRAY_SIZE(uart_config)
130static const spi_conf_t spi_config[] = {
131 {
132 .dev = SPI2,
133 .mosi_pin = GPIO_PIN(PORT_B, 15),
134 .miso_pin = GPIO_PIN(PORT_B, 14),
135 .sclk_pin = GPIO_PIN(PORT_I, 1),
136 .cs_pin = SPI_CS_UNDEF,
137 .mosi_af = GPIO_AF5,
138 .miso_af = GPIO_AF5,
139 .sclk_af = GPIO_AF5,
140 .cs_af = GPIO_AF5,
141 .rccmask = RCC_APB1ENR_SPI2EN,
142 .apbbus = APB1,
143#ifdef MODULE_PERIPH_DMA
144 .tx_dma = 4,
145 .tx_dma_chan = 0,
146 .rx_dma = 3,
147 .rx_dma_chan = 0,
148#endif
149 },
150};
151
152#define SPI_NUMOF ARRAY_SIZE(spi_config)
159static const i2c_conf_t i2c_config[] = {
160 {
161 .dev = I2C1,
162 .speed = I2C_SPEED_NORMAL,
163 .scl_pin = GPIO_PIN(PORT_B, 8),
164 .sda_pin = GPIO_PIN(PORT_B, 9),
165 .scl_af = GPIO_AF4,
166 .sda_af = GPIO_AF4,
167 .bus = APB1,
168 .rcc_mask = RCC_APB1ENR_I2C1EN,
169 .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
170 .irqn = I2C1_ER_IRQn,
171 },
172 {
173 .dev = I2C3,
174 .speed = I2C_SPEED_NORMAL,
175 .scl_pin = GPIO_PIN(PORT_H, 7),
176 .sda_pin = GPIO_PIN(PORT_H, 8),
177 .scl_af = GPIO_AF4,
178 .sda_af = GPIO_AF4,
179 .bus = APB1,
180 .rcc_mask = RCC_APB1ENR_I2C3EN,
181 .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
182 .irqn = I2C3_ER_IRQn,
183 },
184};
185
186#define I2C_0_ISR isr_i2c1_er
187#define I2C_1_ISR isr_i2c3_er
188
189#define I2C_NUMOF ARRAY_SIZE(i2c_config)
196static const eth_conf_t eth_config = {
197 .mode = RMII,
199 .dma = 7,
200 .dma_chan = 8,
201 .phy_addr = 0x00,
202 .pins = {
203 GPIO_PIN(PORT_G, 13), /* TXD0 */
204 GPIO_PIN(PORT_G, 14), /* TXD1 */
205 GPIO_PIN(PORT_G, 11), /* TX_EN */
206 GPIO_PIN(PORT_C, 4), /* RXD0 */
207 GPIO_PIN(PORT_C, 5), /* RXD1 */
208 GPIO_PIN(PORT_A, 7), /* CRS_DV */
209 GPIO_PIN(PORT_C, 1), /* MDC */
210 GPIO_PIN(PORT_A, 2), /* MDIO */
211 GPIO_PIN(PORT_A, 1), /* REF_CLK */
212 }
213};
214
215#define ETH_DMA_ISR isr_dma2_stream0
223static const ltdc_conf_t ltdc_config = {
224 .bus = APB2,
225 .rcc_mask = RCC_APB2ENR_LTDCEN,
226 .clk_pin = { .pin = GPIO_PIN(PORT_I, 14), .af = GPIO_AF14, },
227 .de_pin = { .pin = GPIO_PIN(PORT_K, 7), .af = GPIO_AF14, },
228 .hsync_pin = { .pin = GPIO_PIN(PORT_I, 10), .af = GPIO_AF14, },
229 .vsync_pin = { .pin = GPIO_PIN(PORT_I, 9), .af = GPIO_AF14, },
230 .r_pin = {
231 { .pin = GPIO_PIN(PORT_I, 15), .af = GPIO_AF14, },
232 { .pin = GPIO_PIN(PORT_J, 0), .af = GPIO_AF14, },
233 { .pin = GPIO_PIN(PORT_J, 1), .af = GPIO_AF14, },
234 { .pin = GPIO_PIN(PORT_J, 2), .af = GPIO_AF14, },
235 { .pin = GPIO_PIN(PORT_J, 3), .af = GPIO_AF14, },
236 { .pin = GPIO_PIN(PORT_J, 4), .af = GPIO_AF14, },
237 { .pin = GPIO_PIN(PORT_J, 5), .af = GPIO_AF14, },
238 { .pin = GPIO_PIN(PORT_J, 6), .af = GPIO_AF14, },
239 },
240 .g_pin = {
241 { .pin = GPIO_PIN(PORT_J, 7), .af = GPIO_AF14, },
242 { .pin = GPIO_PIN(PORT_J, 8), .af = GPIO_AF14, },
243 { .pin = GPIO_PIN(PORT_J, 9), .af = GPIO_AF14, },
244 { .pin = GPIO_PIN(PORT_J, 10), .af = GPIO_AF14, },
245 { .pin = GPIO_PIN(PORT_J, 11), .af = GPIO_AF14, },
246 { .pin = GPIO_PIN(PORT_K, 0), .af = GPIO_AF14, },
247 { .pin = GPIO_PIN(PORT_K, 1), .af = GPIO_AF14, },
248 { .pin = GPIO_PIN(PORT_K, 2), .af = GPIO_AF14, },
249 },
250 .b_pin = {
251 { .pin = GPIO_PIN(PORT_E, 4), .af = GPIO_AF14, },
252 { .pin = GPIO_PIN(PORT_J, 13), .af = GPIO_AF14, },
253 { .pin = GPIO_PIN(PORT_J, 14), .af = GPIO_AF14, },
254 { .pin = GPIO_PIN(PORT_J, 15), .af = GPIO_AF14, },
255 { .pin = GPIO_PIN(PORT_G, 12), .af = GPIO_AF9, },
256 { .pin = GPIO_PIN(PORT_K, 4), .af = GPIO_AF14, },
257 { .pin = GPIO_PIN(PORT_K, 5), .af = GPIO_AF14, },
258 { .pin = GPIO_PIN(PORT_K, 6), .af = GPIO_AF14, },
259 },
260 /* values below come from STM32CubeF7 code and differ from the typical
261 * values mentioned in the RK043FN48H datasheet. Both sets of values work
262 * with the display.
263 * See the discussion in
264 * https://community.st.com/s/question/0D50X0000BOvdWP/how-to-set-displays-parameters-
265 */
266 .hsync = 41,
267 .vsync = 10,
268 .hbp = 13,
269 .hfp = 32,
270 .vbp = 2,
271 .vfp = 2,
272};
275#if defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN
288#define DWC2_USB_OTG_HS_ENABLED
289
294 {
295 .periph = USB_OTG_HS_PERIPH_BASE,
296 .type = DWC2_USB_OTG_HS,
298 .rcc_mask = RCC_AHB1ENR_OTGHSEN,
299 .irqn = OTG_HS_IRQn,
300 .ahb = AHB1,
301 .ulpi_af = GPIO_AF10,
302 .ulpi_clk = GPIO_PIN(PORT_A, 5),
303 .ulpi_d0 = GPIO_PIN(PORT_A, 3),
304 .ulpi_d1 = GPIO_PIN(PORT_B, 0),
305 .ulpi_d2 = GPIO_PIN(PORT_B, 1),
306 .ulpi_d3 = GPIO_PIN(PORT_B, 10),
307 .ulpi_d4 = GPIO_PIN(PORT_B, 11),
308 .ulpi_d5 = GPIO_PIN(PORT_B, 12),
309 .ulpi_d6 = GPIO_PIN(PORT_B, 13),
310 .ulpi_d7 = GPIO_PIN(PORT_B, 5),
311 .ulpi_dir = GPIO_PIN(PORT_C, 2),
312 .ulpi_stp = GPIO_PIN(PORT_C, 0),
313 .ulpi_nxt = GPIO_PIN(PORT_H, 4),
314 }
315};
316
320#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
321
323#endif /* defined(MODULE_PERIPH_USBDEV_HS_ULPI) || DOXYGEN */
324
332static const fmc_conf_t fmc_config = {
333 .bus = AHB3,
334 .rcc_mask = RCC_AHB3ENR_FMCEN,
335#if MODULE_PERIPH_FMC_SDRAM
336 .ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* FMC_BA0 signal */
337 .ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* FMC_BA1 signal */
338 .sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* FMC_SDCLK signal */
339 .sdnwe_pin = { .pin = GPIO_PIN(PORT_H, 5), .af = GPIO_AF12, }, /* FMC_SDNWE signal */
340 .sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
341 .sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
342 .sdcke0_pin = { .pin = GPIO_PIN(PORT_C, 3), .af = GPIO_AF12, }, /* FMC_SDCKE0 signal */
343 .sdne0_pin = { .pin = GPIO_PIN(PORT_H, 3), .af = GPIO_AF12, }, /* FMC_SDNE0 signal */
344 .addr = {
345 { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* FMC_A0 signal */
346 { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* FMC_A1 signal */
347 { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* FMC_A2 signal */
348 { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* FMC_A3 signal */
349 { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* FMC_A4 signal */
350 { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* FMC_A5 signal */
351 { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
352 { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
353 { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
354 { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
355 { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* FMC_A10 signal */
356 { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* FMC_A11 signal */
357 },
358#endif
359 .data = {
360 { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
361 { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
362 { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* FMC_D2 signal */
363 { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* FMC_D3 signal */
364 { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* FMC_D4 signal */
365 { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* FMC_D5 signal */
366 { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* FMC_D6 signal */
367 { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
368#if MODULE_PERIPH_FMC_16BIT
369 { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
370 { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
371 { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
372 { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
373 { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
374 { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* FMC_D13 signal */
375 { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* FMC_D14 signal */
376 { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
377#endif
378 },
379 .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (LB) */
380 .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (UB) */
381};
382
395 /* bank 5 is used for SDRAM */
396 {
397 .bank = FMC_BANK_5,
398 .mem_type = FMC_SDRAM,
399 .data_width = FMC_BUS_WIDTH_16BIT,
400 .address = 0xc0000000, /* Bank 5 is mapped to 0xc0000000 */
401 .size = MiB(8), /* Size in MByte, 4M x 16 Bit */
402 .sdram = {
403 .clk_period = 2, /* SDCLK = 2 x HCLK */
404 .row_bits = 12, /* A11..A0 used for row address */
405 .col_bits = 8, /* A7..A0 used for column address */
406 .cas_latency = 2, /* CAS latency is 2 clock cycles */
407 .read_delay = 0, /* No read delay after CAS */
408 .burst_read = true, /* Burst read mode enabled */
409 .burst_write = false, /* Burst write mode disabled */
410 .burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 */
411 .burst_interleaved = false, /* Burst mode interleaved */
412 .write_protect = false, /* No write protection */
413 .four_banks = true, /* SDRAM has four internal banks */
414 .timing = { /* SDRAM Timing parameters */
415 .row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
416 .row_precharge = 2, /* Row precharge delay (2 clock cycles) */
417 .recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
418 .row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
419 .self_refresh = 4, /* Self refresh time is (4 clock cycles) */
420 .exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
421 .load_mode_register = 2, /* Load Mode Register to Activate delay */
422 .refresh_period = 16, /* Refresh period in ms */
423 },
424 },
425 },
426};
427
431#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
442static const sdmmc_conf_t sdmmc_config[] = {
443 {
444 .dev = SDMMC1,
445 .bus = APB2,
446 .rcc_mask = RCC_APB2ENR_SDMMC1EN,
447 .cd = GPIO_PIN(PORT_C, 13),
448 .cd_active = 0, /* CD pin is LOW active */
449 .cd_mode = GPIO_IN_PU, /* Pull-up R12 not soldered by default */
450 .clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
451 .cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
452 .dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
453 .dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
454 .dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
455 .dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
456#ifdef MODULE_PERIPH_DMA
457 .dma = 5,
458 .dma_chan = 4,
459#endif
460 .irqn = SDMMC1_IRQn
461 },
462};
463
467#define SDMMC_CONFIG_NUMOF 1
468
471#ifdef __cplusplus
472}
473#endif
474
475#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ PORT_K
port K
Definition periph_cpu.h:54
@ PORT_H
port H
Definition periph_cpu.h:52
@ PORT_J
port J
Definition periph_cpu.h:53
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
static const sdmmc_conf_t sdmmc_config[]
SDMMC devices.
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
static const fmc_conf_t fmc_config
FMC controller configuration.
static const ltdc_conf_t ltdc_config
LTDC static configuration struct.
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG HS configuration with ULPI HS PHY.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:37
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
@ GPIO_AF9
use alternate function 9
Definition cpu_gpio.h:112
@ GPIO_AF14
use alternate function 14
Definition cpu_gpio.h:117
@ GPIO_AF12
use alternate function 12
Definition cpu_gpio.h:115
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
@ FMC_SDRAM
SDRAM Controller used.
Definition cpu_fmc.h:345
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition cpu_fmc.h:353
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:69
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:73
Interface definition for MII/RMII h.
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
uintptr_t periph
USB peripheral base address.
Ethernet Peripheral configuration.
Definition cpu_eth.h:44
eth_mode_t mode
Select configuration mode.
Definition cpu_eth.h:45
Bank configuration structure.
Definition cpu_fmc.h:360
fmc_bank_t bank
Bank1 .
Definition cpu_fmc.h:361
FMC peripheral configuration.
Definition cpu_fmc.h:278
uint8_t bus
AHB/APB bus.
Definition cpu_fmc.h:279
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
LTDC Peripheral configuration.
Definition cpu_ltdc.h:41
uint8_t bus
APB bus.
Definition cpu_ltdc.h:42
SDMMC slot configuration.
Definition periph_cpu.h:704
gpio_t cd
Card Detect pin (must be GPIO_UNDEF if not connected)
Definition periph_cpu.h:706
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219
#define MiB(x)
A macro to return the bytes in x MiB.
Definition units.h:34
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_ULPI
ULPI for external HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.