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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Eistec AB
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19
20#ifdef __cplusplus
21extern "C"
22{
23#endif
24
29static const clock_config_t clock_config = {
30 /*
31 * This configuration results in the system running with the internal clock
32 * with the following clock frequencies:
33 * Core: 8 MHz
34 * Bus: 8 MHz
35 * Flash: 8 MHz
36 */
37 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0),
38 /* unsure if this RTC load cap configuration is correct */
39 .rtc_clc = RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK,
40 /* Use the 32 kHz system oscillator output as ERCLK32K. */
41 .osc32ksel = SIM_SOPT1_OSC32KSEL(0),
42 .clock_flags =
43 KINETIS_CLOCK_RTCOSC_EN |
44 KINETIS_CLOCK_USE_FAST_IRC |
45 KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
46 KINETIS_CLOCK_MCGIRCLK_STOP_EN |
47 0,
48 /* Using LIRC8M mode by default */
49 .default_mode = KINETIS_MCG_MODE_LIRC8M,
50 /* The crystal connected to EXTAL0 is 32.768 kHz */
51 .erc_range = KINETIS_MCG_ERC_RANGE_LOW,
52 .osc_clc = 0, /* no load cap configuration, rtc_clc overrides this value on KL43Z */
53 .fcrdiv = MCG_SC_FCRDIV(0), /* LIRC_DIV1 divide by 1 => 8 MHz */
54 .lirc_div2 = MCG_MC_LIRC_DIV2(0), /* LIRC_DIV2 divide by 1 => 8 MHz */
55};
56#define CLOCK_CORECLOCK ( 8000000ul)
57#define CLOCK_MCGIRCLK ( 8000000ul)
58#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
60
65#define PIT_NUMOF (1U)
66#define PIT_CONFIG { \
67 { \
68 .prescaler_ch = 0, \
69 .count_ch = 1, \
70 }, \
71}
72#define LPTMR_NUMOF (1U)
73#define LPTMR_CONFIG { \
74 { \
75 .dev = LPTMR0, \
76 .irqn = LPTMR0_IRQn, \
77 .src = 2, \
78 .base_freq = 32768u, \
79 }, \
80 }
81#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
82
83#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
84#define PIT_ISR_0 isr_pit1
85#define LPTMR_ISR_0 isr_lptmr0
87
92static const uart_conf_t uart_config[] = {
93 {
94 .dev = LPUART0,
95 .freq = CLOCK_MCGIRCLK,
96 .pin_rx = GPIO_PIN(PORT_A, 1),
97 .pin_tx = GPIO_PIN(PORT_A, 2),
98 .pcr_rx = PORT_PCR_MUX(2),
99 .pcr_tx = PORT_PCR_MUX(2),
100 .irqn = LPUART0_IRQn,
101 .scgc_addr = &SIM->SCGC5,
102 .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
103 .mode = UART_MODE_8N1,
104 .type = KINETIS_LPUART,
105 },
106};
107#define UART_NUMOF ARRAY_SIZE(uart_config)
108#define LPUART_0_ISR isr_lpuart0
109/* Use MCGIRCLK (internal reference 4 MHz clock) */
110#define LPUART_0_SRC 3
112
117static const adc_conf_t adc_config[] = {
118 /* dev, pin, channel */
119 { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* Arduino A0 */
120 { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* Arduino A1 */
121 { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A2 */
122 { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 4, .avg = ADC_AVG_MAX }, /* Arduino A3 */
123 { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 11, .avg = ADC_AVG_MAX }, /* Arduino A4 */
124 { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A5 */
125};
126
127#define ADC_NUMOF ARRAY_SIZE(adc_config)
128/*
129 * KL43Z ADC reference settings:
130 * 0: VREFH/VREFL external pin pair
131 * 1: VDDA/VSSA supply pins
132 * 2-3: reserved
133 */
134#define ADC_REF_SETTING 0
136
141static const i2c_conf_t i2c_config[] = {
142 {
143 .i2c = I2C0,
144 .scl_pin = GPIO_PIN(PORT_E, 24),
145 .sda_pin = GPIO_PIN(PORT_E, 25),
146 .freq = CLOCK_CORECLOCK,
147 .speed = I2C_SPEED_FAST,
148 .irqn = I2C0_IRQn,
149 .scl_pcr = (PORT_PCR_MUX(5)),
150 .sda_pcr = (PORT_PCR_MUX(5)),
151 },
152 {
153 .i2c = I2C1,
154 .scl_pin = GPIO_PIN(PORT_E, 1),
155 .sda_pin = GPIO_PIN(PORT_E, 0),
156 .freq = CLOCK_CORECLOCK,
157 .speed = I2C_SPEED_FAST,
158 .irqn = I2C1_IRQn,
159 .scl_pcr = (PORT_PCR_MUX(6)),
160 .sda_pcr = (PORT_PCR_MUX(6)),
161 },
162};
163#define I2C_NUMOF ARRAY_SIZE(i2c_config)
164#define I2C_0_ISR isr_i2c0
165#define I2C_1_ISR isr_i2c1
167
168#ifdef __cplusplus
169}
170#endif
171
#define CLOCK_CORECLOCK
Clock configuration.
Definition periph_cpu.h:31
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:278
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition periph_cpu.h:538
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:293
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition periph_cpu.h:373
ADC device configuration.
Definition periph_cpu.h:377
I2C configuration structure.
Definition periph_cpu.h:298
UART device configuration.
Definition periph_cpu.h:217