periph_cpu.h

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/*
 * Copyright (C) 2015-2017 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include "kernel_defines.h"
#include "mutex.h"
 
#include "cpu.h"
#include "cpu_conf.h"
 
#if defined(_SILICON_LABS_32B_SERIES_2)
#include "em_iadc.h"
#else
#include "em_adc.h"
#endif
#include "em_cmu.h"
#include "em_device.h"
#include "em_gpio.h"
#include "em_timer.h"
#include "em_usart.h"
#include "em_wdog.h"
#include "em_rtc.h"
#if defined(_SILICON_LABS_32B_SERIES_0)
#include "em_dac.h"
#elif defined (_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
#include "em_vdac.h"
#endif
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef struct {
    CMU_Clock_TypeDef clk;   
    CMU_Select_TypeDef src;  
} clk_mux_t;
 
typedef struct {
    CMU_Clock_TypeDef clk;   
    CMU_ClkDiv_TypeDef div;  
} clk_div_t;
 
 
#define CPUID_LEN           (8U)
 
#define CLOCK_CORECLOCK     SystemCoreClock
 
#if defined(DAC_COUNT) && DAC_COUNT > 0
typedef struct {
    DAC_TypeDef *dev;       
    DAC_Ref_TypeDef ref;    
    CMU_Clock_TypeDef cmu;  
} dac_conf_t;
 
typedef struct {
    uint8_t dev;            
    uint8_t index;          
} dac_chan_conf_t;
 
#elif defined(VDAC_COUNT) && VDAC_COUNT > 0
typedef struct {
    VDAC_TypeDef *dev;      
    VDAC_Ref_TypeDef ref;   
    CMU_Clock_TypeDef cmu;  
} dac_conf_t;
 
typedef struct {
    uint8_t dev;            
    uint8_t index;          
} dac_chan_conf_t;
#endif
 
/* RTT_MAX_VALUE some are 24bit, some are 32bit */
#if defined(_RTC_CNT_MASK)
#define RTT_MAX_VALUE       _RTC_CNT_MASK        /* mask has all bits set ==> MAX*/
#elif defined(_RTCC_CNT_MASK)
#define RTT_MAX_VALUE       _RTCC_CNT_MASK       /* mask has all bits set ==> MAX*/
#endif
#define RTT_MAX_FREQUENCY   (32768U)             /* in Hz */
#define RTT_MIN_FREQUENCY   (1U)                 /* in Hz */
#define RTT_CLOCK_FREQUENCY (32768U)             /* in Hz, LFCLK*/
 
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO_UNDEF          (0xffffffff)
 
#define GPIO_PIN(x, y)      ((gpio_t) ((x << 4) | y))
 
#define GPIO_MODE(x, y)     ((x << 1) | y)
 
enum {
#if (_GPIO_PORT_A_PIN_COUNT > 0)
    PA = gpioPortA,         
#endif
#if (_GPIO_PORT_B_PIN_COUNT > 0)
    PB = gpioPortB,         
#endif
#if (_GPIO_PORT_C_PIN_COUNT > 0)
    PC = gpioPortC,         
#endif
#if (_GPIO_PORT_D_PIN_COUNT > 0)
    PD = gpioPortD,         
#endif
#if (_GPIO_PORT_E_PIN_COUNT > 0)
    PE = gpioPortE,         
#endif
#if (_GPIO_PORT_F_PIN_COUNT > 0)
    PF = gpioPortF,         
#endif
#if (_GPIO_PORT_G_PIN_COUNT > 0)
    PG = gpioPortG,         
#endif
#if (_GPIO_PORT_H_PIN_COUNT > 0)
    PH = gpioPortH,         
#endif
#if (_GPIO_PORT_I_PIN_COUNT > 0)
    PI = gpioPortI,         
#endif
#if (_GPIO_PORT_J_PIN_COUNT > 0)
    PJ = gpioPortJ,         
#endif
#if (_GPIO_PORT_K_PIN_COUNT > 0)
    PK = gpioPortK          
#endif
};
 
#ifndef DOXYGEN
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN    = GPIO_MODE(gpioModeInput, 0),             
    GPIO_IN_PD = GPIO_MODE(gpioModeInputPull, 0),         
    GPIO_IN_PU = GPIO_MODE(gpioModeInputPull, 1),         
    GPIO_OUT   = GPIO_MODE(gpioModePushPull, 0),          
    GPIO_OD    = GPIO_MODE(gpioModeWiredAnd, 1),          
    GPIO_OD_PU = GPIO_MODE(gpioModeWiredAndPullUp, 1),    
} gpio_mode_t;
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_FALLING = 2,       
    GPIO_RISING = 1,        
    GPIO_BOTH = 3           
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
#if defined(_SILICON_LABS_32B_SERIES_2)
#if defined(_IADC_CFG_DIGAVG_MASK)
#define ADC_MODE(osr, avg, res)  ((osr << 16) | (avg << 8) | res)
#else
#define ADC_MODE(osr, res)  ((osr << 16) | res)
#endif
 
#define ADC_MODE_OSR(mode)       ((mode & 0xff0000) >> 16)
 
#if defined(_IADC_CFG_DIGAVG_MASK)
#define ADC_MODE_AVG(mode)       ((mode & 0x00ff00) >> 8)
#endif
 
#define ADC_MODE_RES(mode)       ((mode & 0x0000ff) >> 0)
 
#define HAVE_ADC_RES_T
#if defined(_IADC_CFG_DIGAVG_MASK)
typedef enum {
    ADC_RES_6BIT  = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 6),
    ADC_RES_8BIT  = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 8),
    ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 10),
    ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, iadcDigitalAverage1, 12),
    ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, iadcDigitalAverage1, 14),
    ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed16x, iadcDigitalAverage2, 16),
} adc_res_t;
#else
typedef enum {
    ADC_RES_6BIT  = ADC_MODE(iadcCfgOsrHighSpeed2x, 6),
    ADC_RES_8BIT  = ADC_MODE(iadcCfgOsrHighSpeed2x, 8),
    ADC_RES_10BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 10),
    ADC_RES_12BIT = ADC_MODE(iadcCfgOsrHighSpeed2x, 12),
    ADC_RES_14BIT = ADC_MODE(iadcCfgOsrHighSpeed8x, 14),
    ADC_RES_16BIT = ADC_MODE(iadcCfgOsrHighSpeed32x, 16),
} adc_res_t;
#endif
 
typedef struct {
    IADC_TypeDef *dev;
 
    CMU_Clock_TypeDef cmu;
 
    IADC_CfgReference_t reference;
 
    uint32_t reference_mV;
 
    IADC_CfgAnalogGain_t gain;
 
    adc_res_t available_res[IADC0_CONFIGNUM];
} adc_conf_t;
 
typedef struct {
    uint8_t dev;
 
    gpio_t input_pos;
 
    gpio_t input_neg;
} adc_chan_conf_t;
#else  /* defined(_SILICON_LABS_32B_SERIES_2) */
#define ADC_MODE(x, y)      ((y << 4) | x)
 
#define ADC_MODE_UNDEF(x)   (ADC_MODE(x, 15))
 
#ifndef DOXYGEN
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = ADC_MODE(adcRes6Bit, 0),    
    ADC_RES_8BIT  = ADC_MODE(adcRes8Bit, 0),    
    ADC_RES_10BIT = ADC_MODE(adcRes12Bit, 2),   
    ADC_RES_12BIT = ADC_MODE(adcRes12Bit, 0),   
    ADC_RES_14BIT = ADC_MODE_UNDEF(0),          
    ADC_RES_16BIT = ADC_MODE_UNDEF(1),          
} adc_res_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    ADC_TypeDef *dev;                 
    CMU_Clock_TypeDef cmu;            
} adc_conf_t;
 
typedef struct {
    uint8_t dev;                      
#if defined(_SILICON_LABS_32B_SERIES_0)
    ADC_SingleInput_TypeDef input;    
#elif defined(_SILICON_LABS_32B_SERIES_1)
    ADC_PosSel_TypeDef input;         
#endif
    ADC_Ref_TypeDef reference;        
    ADC_AcqTime_TypeDef acq_time;     
} adc_chan_conf_t;
#endif  /* !defined(_SILICON_LABS_32B_SERIES_2) */
 
#define HAVE_HWCRYPTO_AES128
#ifdef AES_CTRL_AES256
#define HAVE_HWCRYPTO_AES256
#endif
#if defined(_SILICON_LABS_32B_SERIES_1)
#define HAVE_HWCRYPTO_SHA1
#define HAVE_HWCRYPTO_SHA256
#endif
#ifndef DOXYGEN
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW = 10000,            
    I2C_SPEED_NORMAL = 100000,        
    I2C_SPEED_FAST = 400000,          
    I2C_SPEED_FAST_PLUS = 1000000,    
    I2C_SPEED_HIGH = 3400000,         
} i2c_speed_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    I2C_TypeDef *dev;       
    gpio_t sda_pin;         
    gpio_t scl_pin;         
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
    uint32_t loc;           
#endif
    CMU_Clock_TypeDef cmu;  
    IRQn_Type irq;          
    uint32_t speed;         
} i2c_conf_t;
 
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_WRITE_REG
#ifndef DOXYGEN
#define HAVE_PWM_MODE_T
typedef enum {
    PWM_LEFT = timerModeUp,           /*< use left aligned PWM */
    PWM_RIGHT = timerModeDown,        /*< use right aligned PWM */
    PWM_CENTER = timerModeUp          /*< not supported, use left aligned */
} pwm_mode_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    uint8_t index;          
    gpio_t pin;             
    uint32_t loc;           
} pwm_chan_conf_t;
 
typedef struct {
    TIMER_TypeDef *dev;               
    CMU_Clock_TypeDef cmu;            
    IRQn_Type irq;                    
    uint8_t channels;                 
    const pwm_chan_conf_t* channel;   
} pwm_conf_t;
 
#ifndef DOXYGEN
#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = usartClockMode0,
    SPI_MODE_1 = usartClockMode1,
    SPI_MODE_2 = usartClockMode2,
    SPI_MODE_3 = usartClockMode3
} spi_mode_t;
#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ = 100000,          
    SPI_CLK_400KHZ = 400000,          
    SPI_CLK_1MHZ = 1000000,           
    SPI_CLK_5MHZ = 5000000,           
    SPI_CLK_10MHZ = 10000000          
} spi_clk_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    USART_TypeDef *dev;     
    gpio_t mosi_pin;        
    gpio_t miso_pin;        
    gpio_t clk_pin;         
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
    uint32_t loc;           
#endif
    CMU_Clock_TypeDef cmu;  
    IRQn_Type irq;          
} spi_dev_t;
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
typedef struct {
    void *dev;              
    CMU_Clock_TypeDef cmu;  
} timer_dev_t;
#endif
 
typedef struct {
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
    timer_dev_t prescaler;  
    timer_dev_t timer;      
    IRQn_Type irq;          
    uint8_t channel_numof;  
#else
    void *dev;              
    CMU_Clock_TypeDef cmu;  
    IRQn_Type irq;          
#endif
} timer_conf_t;
 
#define LETIMER_MAX_VALUE _LETIMER_TOP_MASK  
#define TIMER_MAX_VALUE _TIMER_TOP_MASK      
#ifndef CONFIG_EFM32_XTIMER_USE_LETIMER
#define CONFIG_EFM32_XTIMER_USE_LETIMER   0
#endif
 
#ifndef DOXYGEN
#define UART_MODE_UNSUPPORTED 0xf0
 
#define HAVE_UART_PARITY_T
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
typedef enum {
    UART_PARITY_NONE = 0,
    UART_PARITY_ODD = 1,
    UART_PARITY_EVEN = 2,
    UART_PARITY_MARK = 3,
    UART_PARITY_SPACE = 4,
} uart_parity_t;
#else
typedef enum {
    UART_PARITY_NONE = 0,
    UART_PARITY_EVEN = 2,
    UART_PARITY_ODD = 3,
    UART_PARITY_MARK = UART_MODE_UNSUPPORTED | 0,
    UART_PARITY_SPACE = UART_MODE_UNSUPPORTED | 1,
} uart_parity_t;
#endif
#define HAVE_UART_DATA_BITS_T
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
typedef enum {
    UART_DATA_BITS_5 = 5,
    UART_DATA_BITS_6 = 6,
    UART_DATA_BITS_7 = 7,
    UART_DATA_BITS_8 = 8,
} uart_data_bits_t;
#else
typedef enum {
    UART_DATA_BITS_5 = UART_MODE_UNSUPPORTED | 0,
    UART_DATA_BITS_6 = UART_MODE_UNSUPPORTED | 1,
    UART_DATA_BITS_7 = 1,
    UART_DATA_BITS_8 = 2,
} uart_data_bits_t;
#endif
#define HAVE_UART_STOP_BITS_T
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1)
typedef enum {
   UART_STOP_BITS_1 = 2,
   UART_STOP_BITS_2 = 4,
} uart_stop_bits_t;
#else
typedef enum {
   UART_STOP_BITS_1 = 1,
   UART_STOP_BITS_2 = 3,
} uart_stop_bits_t;
#endif
#endif /* ndef DOXYGEN */
 
typedef struct {
    void *dev;              
    gpio_t rx_pin;          
    gpio_t tx_pin;          
#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
    uint32_t loc;           
#endif
    CMU_Clock_TypeDef cmu;  
    IRQn_Type irq;          
} uart_conf_t;
 
#define PROVIDES_PM_OFF
 
#define PROVIDES_PM_LAYERED_OFF
 
#define PM_NUM_MODES    (3U)
 
#define EFM32_PM_MODE_EM3  (0U)  
#define EFM32_PM_MODE_EM2  (1U)  
#define EFM32_PM_MODE_EM1  (2U)  
#define WDT_CLOCK_HZ            (1000U)
 
#define NWDT_TIME_LOWER_LIMIT   ((1U << (3U + wdogPeriod_9)) + 1U)
#define NWDT_TIME_UPPER_LIMIT   ((1U << (3U + wdogPeriod_256k)) + 1U)
 
#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2)
#define WDT_TIME_LOWER_LIMIT    NWDT_TIME_LOWER_LIMIT
#define WDT_TIME_UPPER_LIMIT    NWDT_TIME_UPPER_LIMIT
#endif
 
#define WDT_HAS_STOP            (1U)
#define USBDEV_NUM_ENDPOINTS    7   
/* GPIO_LL's overrides */
#ifndef DOXYGEN
 
/* Not supported by hardware */
#define HAVE_GPIO_SLEW_T
typedef enum {
    GPIO_SLEW_SLOWEST = 0,
    GPIO_SLEW_SLOW = 0,
    GPIO_SLEW_FAST = 0,
    GPIO_SLEW_FASTEST = 0,
} gpio_slew_t;
 
/* Not supported by hardware */
#define HAVE_GPIO_PULL_STRENGTH_T
typedef enum {
    GPIO_PULL_WEAKEST = 0,
    GPIO_PULL_WEAK = 0,
    GPIO_PULL_STRONG = 0,
    GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
 
/* Not implemented, see gpio_ll_arch.h comments */
#define HAVE_GPIO_DRIVE_STRENGTH_T
typedef enum {
    GPIO_DRIVE_WEAKEST = 0,
    GPIO_DRIVE_WEAK = 0,
    GPIO_DRIVE_STRONG = 0,
    GPIO_DRIVE_STRONGEST = 0
} gpio_drive_strength_t;
 
#endif
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */