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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2024 ML!PA Consulting GmbH
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "periph_cpu.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
29#ifndef CLOCK_CORECLOCK
30#define CLOCK_CORECLOCK MHZ(120)
31#endif
33
38#define EXTERNAL_OSC32_SOURCE 1
39#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
41
46#define USE_VREG_BUCK (1)
47
52static const tc32_conf_t timer_config[] = {
53 { /* Timer 0 - System Clock */
54 .dev = TC0,
55 .irq = TC0_IRQn,
56 .mclk = &MCLK->APBAMASK.reg,
57 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
58 .gclk_id = TC0_GCLK_ID,
59 .gclk_src = SAM0_GCLK_TIMER,
60 .flags = TC_CTRLA_MODE_COUNT32,
61 },
62 { /* Timer 1 */
63 .dev = TC2,
64 .irq = TC2_IRQn,
65 .mclk = &MCLK->APBBMASK.reg,
66 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
67 .gclk_id = TC2_GCLK_ID,
68 .gclk_src = SAM0_GCLK_TIMER,
69 .flags = TC_CTRLA_MODE_COUNT32,
70 }
71};
72
73/* Timer 0 configuration */
74#define TIMER_0_CHANNELS 2
75#define TIMER_0_ISR isr_tc0
76
77/* Timer 1 configuration */
78#define TIMER_1_CHANNELS 2
79#define TIMER_1_ISR isr_tc2
80
81#define TIMER_NUMOF ARRAY_SIZE(timer_config)
83
89static const can_conf_t candev_conf[] = {
90 {
91 .can = CAN0,
92 .rx_pin = GPIO_PIN(PA, 22),
93 .tx_pin = GPIO_PIN(PB, 23),
94 .gclk_src = SAM0_GCLK_PERIPH,
95 },
96 {
97 .can = CAN1,
98 .rx_pin = GPIO_PIN(PB, 15),
99 .tx_pin = GPIO_PIN(PB, 14),
100 .gclk_src = SAM0_GCLK_PERIPH,
101 }
102};
103
105#define ISR_CAN0 isr_can0
106
108#define ISR_CAN1 isr_can1
109
111#define CAN_NUMOF ARRAY_SIZE(candev_conf)
113
118static const uart_conf_t uart_config[] = {
119 { /* Virtual COM Port */
120 .dev = &SERCOM5->USART,
121 .rx_pin = GPIO_PIN(PB, 16),
122 .tx_pin = GPIO_PIN(PB, 17),
123 .mux = GPIO_MUX_C,
124 .rx_pad = UART_PAD_RX_1,
125 .tx_pad = UART_PAD_TX_0,
126 .flags = UART_FLAG_NONE,
127 .gclk_src = SAM0_GCLK_PERIPH,
128 },
129 { /* shared with CAN1 */
130 .dev = &SERCOM4->USART,
131 .rx_pin = GPIO_PIN(PB, 13),
132 .tx_pin = GPIO_PIN(PB, 12),
133#ifdef MODULE_PERIPH_UART_HW_FC
134 .rts_pin = GPIO_PIN(PB, 14),
135 .cts_pin = GPIO_PIN(PB, 15),
136#endif
137 .mux = GPIO_MUX_C,
138 .rx_pad = UART_PAD_RX_1,
139#ifdef MODULE_PERIPH_UART_HW_FC
141#else
142 .tx_pad = UART_PAD_TX_0,
143#endif
144 .flags = UART_FLAG_NONE,
145 .gclk_src = SAM0_GCLK_PERIPH,
146 },
147 {
148 .dev = &SERCOM0->USART,
149 .rx_pin = GPIO_PIN(PA, 9),
150 .tx_pin = GPIO_PIN(PA, 8),
151#ifdef MODULE_PERIPH_UART_HW_FC
152 .rts_pin = GPIO_PIN(PA, 10),
153 .cts_pin = GPIO_PIN(PA, 10),
154#endif
155 .mux = GPIO_MUX_C,
156 .rx_pad = UART_PAD_RX_1,
157#ifdef MODULE_PERIPH_UART_HW_FC
159#else
160 .tx_pad = UART_PAD_TX_0,
161#endif
162 .flags = UART_FLAG_NONE,
163 .gclk_src = SAM0_GCLK_PERIPH,
164 },
165 { /* shared with CAN0 */
166 .dev = &SERCOM3->USART,
167 .rx_pin = GPIO_PIN(PA, 23),
168 .tx_pin = GPIO_PIN(PA, 22),
169 .mux = GPIO_MUX_C,
170 .rx_pad = UART_PAD_RX_1,
171 .tx_pad = UART_PAD_TX_0,
172 .flags = UART_FLAG_NONE,
173 .gclk_src = SAM0_GCLK_PERIPH,
174 }
175};
176
177/* interrupt function name mapping */
178#define UART_0_ISR isr_sercom5_2
179#define UART_0_ISR_TX isr_sercom5_0
180
181#define UART_1_ISR isr_sercom4_2
182#define UART_1_ISR_TX isr_sercom4_0
183
184#define UART_2_ISR isr_sercom0_2
185#define UART_2_ISR_TX isr_sercom0_0
186
187#define UART_3_ISR isr_sercom3_2
188#define UART_3_ISR_TX isr_sercom3_0
189
190#define UART_NUMOF ARRAY_SIZE(uart_config)
192
197
198/* PWM0 channels */
199static const pwm_conf_chan_t pwm_chan0_config[] = {
200 /* GPIO pin, MUX value, TCC channel */
201 {
202 .pin = GPIO_PIN(PA, 14), /* LED0 */
203 .mux = GPIO_MUX_F,
204 .chan = 0,
205 },
206};
207
208/* PWM device configuration */
209static const pwm_conf_t pwm_config[] = {
210 {
211 .tim = TCC_CONFIG(TCC2),
212 .chan = pwm_chan0_config,
213 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
214 .gclk_src = SAM0_GCLK_48MHZ,
215 },
216};
217
218/* number of devices that are actually defined */
219#define PWM_NUMOF ARRAY_SIZE(pwm_config)
221
226static const spi_conf_t spi_config[] = {
227 {
228 .dev = &SERCOM1->SPI,
229 .miso_pin = GPIO_PIN(PA, 19),
230 .mosi_pin = GPIO_PIN(PA, 16),
231 .clk_pin = GPIO_PIN(PA, 27),
232 .miso_mux = GPIO_MUX_C,
233 .mosi_mux = GPIO_MUX_C,
234 .clk_mux = GPIO_MUX_C,
235 .miso_pad = SPI_PAD_MISO_3,
236 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
237 .gclk_src = SAM0_GCLK_PERIPH,
238#ifdef MODULE_PERIPH_DMA
239 .tx_trigger = SERCOM1_DMAC_ID_TX,
240 .rx_trigger = SERCOM1_DMAC_ID_RX,
241#endif
242
243 },
244};
245
246#define SPI_NUMOF ARRAY_SIZE(spi_config)
248
253static const i2c_conf_t i2c_config[] = {
254 {
255 .dev = &SERCOM2->I2CM,
256 .speed = I2C_SPEED_NORMAL,
257 .scl_pin = GPIO_PIN(PA, 13),
258 .sda_pin = GPIO_PIN(PA, 12),
259 .mux = GPIO_MUX_C,
260 .gclk_src = SAM0_GCLK_PERIPH,
261 .flags = I2C_FLAG_NONE
262 },
263};
264
265#define I2C_NUMOF ARRAY_SIZE(i2c_config)
267
272#ifndef RTT_FREQUENCY
273#define RTT_FREQUENCY (32768U)
274#endif
276
283static const sam0_common_usb_config_t sam_usbdev_config[] = {
284 {
285 .dm = GPIO_PIN(PA, 24),
286 .dp = GPIO_PIN(PA, 25),
287 .d_mux = GPIO_MUX_H,
288 .device = &USB->DEVICE,
289 .gclk_src = SAM0_GCLK_PERIPH,
290 }
291};
293
298
299/* ADC Default values */
300#define ADC_GCLK_SRC SAM0_GCLK_PERIPH
301#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
302
303#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
304#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
305
306static const adc_conf_chan_t adc_channels[] = {
307 /* inputctrl, dev */
308 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA07, .dev = ADC0 },
309 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 },
310 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 },
311 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA11, .dev = ADC0 },
312 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA10, .dev = ADC0 },
313 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 },
314 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB03, .dev = ADC0 },
315 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 },
316 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB04, .dev = ADC1 },
317 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB05, .dev = ADC1 },
318 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB06, .dev = ADC1 },
319 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB07, .dev = ADC1 },
320 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB01, .dev = ADC0 },
321 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB00, .dev = ADC0 },
322 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA03, .dev = ADC0 },
323};
324
325#define ADC_NUMOF ARRAY_SIZE(adc_channels)
327
332 /* Must not exceed 12 MHz */
333#define DAC_CLOCK SAM0_GCLK_TIMER
334 /* Use external reference voltage on PA03 */
335 /* (You have to manually connect PA03 with Vcc) */
336 /* Internal reference only gives 1V */
337#define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
339
340#ifdef __cplusplus
341}
342#endif
343
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:82
@ UART_PAD_RX_1
select pad 1
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PA
port A
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_F
select peripheral function F
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition periph_cpu.h:129
#define ADC0_INPUTCTRL_MUXPOS_PA07
Alias for AIN7.
Definition periph_cpu.h:132
#define ADC0_INPUTCTRL_MUXPOS_PA10
Alias for AIN10.
Definition periph_cpu.h:135
#define ADC1_INPUTCTRL_MUXPOS_PB05
Alias for AIN7.
Definition periph_cpu.h:149
#define ADC1_INPUTCTRL_MUXPOS_PB04
Alias for AIN6.
Definition periph_cpu.h:148
#define ADC0_INPUTCTRL_MUXPOS_PB01
Alias for AIN13.
Definition periph_cpu.h:138
#define ADC0_INPUTCTRL_MUXPOS_PB03
Alias for AIN15.
Definition periph_cpu.h:140
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition periph_cpu.h:127
#define ADC0_INPUTCTRL_MUXPOS_PA11
Alias for AIN11.
Definition periph_cpu.h:136
#define ADC0_INPUTCTRL_MUXPOS_PB00
Alias for AIN12.
Definition periph_cpu.h:137
#define ADC1_INPUTCTRL_MUXPOS_PB07
Alias for AIN9.
Definition periph_cpu.h:151
#define ADC0_INPUTCTRL_MUXPOS_PA03
Alias for AIN1.
Definition periph_cpu.h:126
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition periph_cpu.h:128
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:78
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:125
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:81
#define ADC1_INPUTCTRL_MUXPOS_PB06
Alias for AIN8.
Definition periph_cpu.h:150
ADC Channel Configuration.
ESP CAN device configuration.
Definition can_esp.h:87
Linux candev configuration.
I2C configuration structure.
Definition periph_cpu.h:298
PWM channel configuration data structure.
PWM device configuration.
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
UART device configuration.
Definition periph_cpu.h:217