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cc26xx_cc13xx_i2c.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2016 Leon George
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef CC26XX_CC13XX_I2C_H
20#define CC26XX_CC13XX_I2C_H
21
22#include "cc26xx_cc13xx.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
56
62#define MCR_MFE 0x00000010
63
77#define MTPR_TPR_100KHZ 0x00000017
78
86#define MSA_RS 0x00000001
87
95#define MSTAT_BUSBSY 0x00000040
96
102#define MSTAT_IDLE 0x00000020
103
109#define MSTAT_ARBLST 0x00000010
110
116#define MSTAT_DATACK_N 0x00000008
117
123#define MSTAT_ADRACK_N 0x00000004
124
130#define MSTAT_ERR 0x00000002
131
145#define MSTAT_BUSY 0x00000001
146
158#define MCTRL_ACK 0x00000008
159
168#define MCTRL_STOP 0x00000004
169
177#define MCTRL_START 0x00000002
178
186#define MCTRL_RUN 0x00000001
187
192#define I2C_BASE (PERIPH_BASE + 0x2000)
195#define I2C ((i2c_regs_t *) (I2C_BASE))
197#ifdef __cplusplus
198}
199#endif
200
201#endif /* CC26XX_CC13XX_I2C_H */
CC26xx, CC13xx definitions.
volatile uint32_t reg32_t
Unsigned 32-bit register type.
I2C registers.
reg32_t SMIS
slave masked interrupt status
reg32_t SICR
slave interrupt clear
reg32_t SIMR
slave interrupt mask
reg32_t SRIS
slave raw interrupt status
reg32_t MCR
master configuration
reg32_t MCTRL
master control
reg32_t SCTL
slave control
reg32_t MRIS
master raw interrupt status
reg32_t MDR
master data
reg32_t SSTAT
slave status
reg32_t MSA
master slave address
reg32_t MIMR
master interrupt mask
reg32_t MTPR
master timer period
reg32_t MMIS
master masked interrupt statues
reg32_t SDR
slave data
reg32_t SOAR
slave own address
reg32_t MICR
master interrupt clear
reg32_t MSTAT
master status