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cfg_usb_otg_fs.h
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1/*
2 * Copyright (C) 2019 Koen Zandberg
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef CFG_USB_OTG_FS_H
20#define CFG_USB_OTG_FS_H
21
22#include "periph_cpu.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
32#define DWC2_USB_OTG_FS_ENABLED
33
38 {
39 .periph = USB_OTG_FS_PERIPH_BASE,
40 .type = DWC2_USB_OTG_FS,
42 .rcc_mask = RCC_AHB2ENR_OTGFSEN,
43 .irqn = OTG_FS_IRQn,
44 .ahb = AHB2,
45 .dm = GPIO_PIN(PORT_A, 11),
46 .dp = GPIO_PIN(PORT_A, 12),
47 .af = GPIO_AF10,
48 }
49};
50
54#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
55
56#ifdef __cplusplus
57}
58#endif
59
60#endif /* CFG_USB_OTG_FS_H */
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
uintptr_t periph
USB peripheral base address.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_BUILTIN
on-chip FS PHY
@ DWC2_USB_OTG_FS
Full speed peripheral.