Default STM32U3 clock configuration (bring-up) More...

Detailed Description

Default STM32U3 clock configuration (bring-up)

This configuration is intentionally conservative for early bring-up. By default it uses HSI (16 MHz) as SYSCLK and disables PLL usage.

Author: Adarsh Nair Mullachery adars.nosp@m.h.mu.nosp@m.llach.nosp@m.ery@.nosp@m.tuhh..nosp@m.de

Definition in file cfg_clock_default.h.

#include "cfg_clock_common_lx_u5_wx.h"
#include "kernel_defines.h"
#include "macros/units.h"

Include dependency graph for cfg_clock_default.h:

Go to the source code of this file.

Clock system configuration (STM32U3)
#define	CONFIG_USE_CLOCK_PLL 0
	Set to 1 to use the PLL as system clock source (STM32U3 has no main PLL)

#define	CONFIG_USE_CLOCK_HSI 1
	Set to 1 to use HSI as system clock source (default for bring-up)

#define	CONFIG_CLOCK_HSI MHZ(16)
	HSI (high-speed internal) oscillator frequency.

#define	CONFIG_CLOCK_HSE MHZ(8)
	HSE (high-speed external) oscillator frequency.

#define	CONFIG_CLOCK_MSI MHZ(12)
	MSIS (multi-speed internal) oscillator frequency, used when MSI is selected.

#define	CLOCK_CORECLOCK CONFIG_CLOCK_HSI

#define	CLOCK_CORECLOCK_MAX MHZ(96)
	Maximum system core clock (SYSCLK) allowed on the STM32U3.

#define	CLOCK_AHB CLOCK_CORECLOCK

#define	CONFIG_CLOCK_APB1_DIV (1)

#define	CONFIG_CLOCK_APB2_DIV (1)

#define	CONFIG_CLOCK_APB3_DIV (1)

#define	CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV)

#define	CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV)

#define	CLOCK_APB3 (CLOCK_AHB / CONFIG_CLOCK_APB3_DIV)
	APB3 peripheral clock.

Macro Definition Documentation

◆ CLOCK_AHB

#define CLOCK_AHB CLOCK_CORECLOCK

Definition at line 73 of file cfg_clock_default.h.

◆ CLOCK_APB1

#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV)

Definition at line 87 of file cfg_clock_default.h.

◆ CLOCK_APB2

#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV)

Definition at line 88 of file cfg_clock_default.h.

◆ CLOCK_APB3

#define CLOCK_APB3 (CLOCK_AHB / CONFIG_CLOCK_APB3_DIV)

APB3 peripheral clock.

Definition at line 90 of file cfg_clock_default.h.

◆ CLOCK_CORECLOCK

#define CLOCK_CORECLOCK CONFIG_CLOCK_HSI

Definition at line 63 of file cfg_clock_default.h.

◆ CLOCK_CORECLOCK_MAX

#define CLOCK_CORECLOCK_MAX MHZ(96)

Maximum system core clock (SYSCLK) allowed on the STM32U3.

Definition at line 67 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_APB1_DIV

#define CONFIG_CLOCK_APB1_DIV (1)

Definition at line 76 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_APB2_DIV

#define CONFIG_CLOCK_APB2_DIV (1)

Definition at line 80 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_APB3_DIV

#define CONFIG_CLOCK_APB3_DIV (1)

Definition at line 84 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_HSE

#define CONFIG_CLOCK_HSE MHZ(8)

HSE (high-speed external) oscillator frequency.

Definition at line 50 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_HSI

#define CONFIG_CLOCK_HSI MHZ(16)

HSI (high-speed internal) oscillator frequency.

Definition at line 45 of file cfg_clock_default.h.

◆ CONFIG_CLOCK_MSI

#define CONFIG_CLOCK_MSI MHZ(12)

MSIS (multi-speed internal) oscillator frequency, used when MSI is selected.

Definition at line 55 of file cfg_clock_default.h.

◆ CONFIG_USE_CLOCK_HSI

#define CONFIG_USE_CLOCK_HSI 1

Set to 1 to use HSI as system clock source (default for bring-up)

Definition at line 40 of file cfg_clock_default.h.

◆ CONFIG_USE_CLOCK_PLL

#define CONFIG_USE_CLOCK_PLL 0

Set to 1 to use the PLL as system clock source (STM32U3 has no main PLL)

Definition at line 35 of file cfg_clock_default.h.