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periph_cpu.h
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1/*
2 * Copyright (C) 2015-2016 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CPU_H
21#define PERIPH_CPU_H
22
23#include "periph_cpu_common.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
32#define CPU_BACKUP_RAM_NOT_RETAINED (1)
33
38#define PM_NUM_MODES (3)
39#define SAML21_PM_MODE_BACKUP (0)
40#define SAML21_PM_MODE_STANDBY (1)
41#define SAML21_PM_MODE_IDLE (2)
48#define SAM0_GPIO_PM_BLOCK SAML21_PM_MODE_BACKUP
49#define SAM0_RTCRTT_PM_BLOCK SAML21_PM_MODE_BACKUP
50#define SAM0_SPI_PM_BLOCK SAML21_PM_MODE_STANDBY
51#define SAM0_TIMER_PM_BLOCK SAML21_PM_MODE_STANDBY
52#define SAM0_UART_PM_BLOCK SAML21_PM_MODE_STANDBY
53#define SAM0_USB_IDLE_PM_BLOCK SAML21_PM_MODE_BACKUP
54#define SAM0_USB_ACTIVE_PM_BLOCK SAML21_PM_MODE_STANDBY
61#ifndef PM_BLOCKER_INITIAL
62#define PM_BLOCKER_INITIAL { 0, 0, 0 }
63#endif
64
69enum {
74};
80static const gpio_t sam0_adc_pins[1][20] = {
81 {
82 GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8), GPIO_PIN(PB, 9),
83 GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6), GPIO_PIN(PA, 7),
84 GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2), GPIO_PIN(PB, 3),
85 GPIO_PIN(PB, 4), GPIO_PIN(PB, 5), GPIO_PIN(PB, 6), GPIO_PIN(PB, 7),
86 GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
87 }
88};
89
94#define ADC_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
95#define ADC_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
96#define ADC_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN2
97#define ADC_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN3
98#define ADC_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN4
99#define ADC_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN5
100#define ADC_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN6
101#define ADC_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN7
102#define ADC_INPUTCTRL_MUXPOS_PB00 ADC_INPUTCTRL_MUXPOS_AIN8
103#define ADC_INPUTCTRL_MUXPOS_PB01 ADC_INPUTCTRL_MUXPOS_AIN9
104#define ADC_INPUTCTRL_MUXPOS_PB02 ADC_INPUTCTRL_MUXPOS_AIN10
105#define ADC_INPUTCTRL_MUXPOS_PB03 ADC_INPUTCTRL_MUXPOS_AIN11
106#define ADC_INPUTCTRL_MUXPOS_PB04 ADC_INPUTCTRL_MUXPOS_AIN12
107#define ADC_INPUTCTRL_MUXPOS_PB05 ADC_INPUTCTRL_MUXPOS_AIN13
108#define ADC_INPUTCTRL_MUXPOS_PB06 ADC_INPUTCTRL_MUXPOS_AIN14
109#define ADC_INPUTCTRL_MUXPOS_PB07 ADC_INPUTCTRL_MUXPOS_AIN15
110#define ADC_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN16
111#define ADC_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN17
112#define ADC_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN18
113#define ADC_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN19
115#define ADC_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
116#define ADC_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
117#define ADC_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN2
118#define ADC_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN3
119#define ADC_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN4
120#define ADC_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN5
121#define ADC_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN6
122#define ADC_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN7
128#define DAC_RES_BITS (12)
129
133#define DAC_NUMOF (2)
134
139#define RTT_MAX_VALUE (0xffffffff)
140#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
141#define RTT_MIN_FREQUENCY (RTT_CLOCK_FREQUENCY / 512U) /* in Hz */
142#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
143/* determined by tests/sys/ztimer_underflow */
144#define RTT_MIN_OFFSET (8U)
153 uint64_t bootloader_size : 3;
154 uint64_t reserved_0 : 1;
155 uint64_t eeprom_size : 3;
156 uint64_t reserved_1 : 1;
157 uint64_t bod33_level : 6;
158 uint64_t bod33_enable : 1;
159 uint64_t bod33_action : 2;
160 uint64_t reserved_2 : 9;
161 uint64_t wdt_enable : 1;
162 uint64_t wdt_always_on : 1;
163 uint64_t wdt_period : 4;
164 uint64_t wdt_window : 4;
165 uint64_t wdt_ewoffset : 4;
166 uint64_t wdt_window_enable : 1;
167 uint64_t bod33_hysteresis : 1;
168 uint64_t reserved_3 : 6;
169 uint64_t nvm_locks : 16;
170};
173#ifdef __cplusplus
174}
175#endif
176
177#endif /* PERIPH_CPU_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ PB
port B
@ PA
port A
@ SAM0_GCLK_MAIN
48 MHz main clock
Definition periph_cpu.h:75
@ SAM0_GCLK_32KHZ
32 kHz clock
Definition periph_cpu.h:77
static const gpio_t sam0_adc_pins[1][20]
Pins that can be used for ADC input.
Definition periph_cpu.h:105
@ SAM0_GCLK_TIMER
4/8MHz clock for timers
Definition periph_cpu.h:71
@ SAM0_GCLK_48MHZ
48MHz clock
Definition periph_cpu.h:73
NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on.
Definition periph_cpu.h:177
uint64_t bod33_level
BOD33 threshold level at power-on.
Definition periph_cpu.h:182
uint64_t wdt_window
WDT Window at power-on.
Definition periph_cpu.h:189
uint64_t wdt_window_enable
WDT Window mode enabled on power-on
Definition periph_cpu.h:191
uint64_t nvm_locks
NVM Region Lock Bits.
Definition periph_cpu.h:195
uint64_t bod33_hysteresis
BOD33 Hysteresis configuration
Definition periph_cpu.h:192
uint64_t bod33_action
BOD33 Action at power-on.
Definition periph_cpu.h:184
uint64_t bod33_enable
BOD33 Enable at power-on.
Definition periph_cpu.h:183
uint64_t wdt_period
WDT Period at power-on.
Definition periph_cpu.h:188
uint64_t reserved_2
Factory settings - do not change.
Definition periph_cpu.h:185
uint64_t bootloader_size
BOOTPROT: Bootloader Size
Definition periph_cpu.h:178
uint64_t wdt_ewoffset
WDT Early Warning Interrupt Offset
Definition periph_cpu.h:190
uint64_t eeprom_size
one of eight different EEPROM sizes
Definition periph_cpu.h:180
uint64_t reserved_0
Factory settings - do not change.
Definition periph_cpu.h:179
uint64_t reserved_1
Factory settings - do not change.
Definition periph_cpu.h:181
uint64_t wdt_always_on
WDT Always-On at power-on.
Definition periph_cpu.h:187
uint64_t reserved_3
Factory settings - do not change.
Definition periph_cpu.h:194
uint64_t wdt_enable
WDT Enable at power-on.
Definition periph_cpu.h:186