Internal addresses, registers, constants for the Si1133 sensors family.
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Internal addresses, registers, constants for the Si1133 sensors family.
Internal addresses, registers, constants for the Si1133 sensor.
- Author
- iosabi iosab.nosp@m.i@pr.nosp@m.otonm.nosp@m.ail..nosp@m.com
Definition in file si1133_internals.h.
#include <stdint.h>
Go to the source code of this file.
◆ SI1133_ADCCONFIG_ADCMUX_MASK
#define SI1133_ADCCONFIG_ADCMUX_MASK (0x1f) |
◆ SI1133_ADCCONFIG_ADCMUX_SHIFT
#define SI1133_ADCCONFIG_ADCMUX_SHIFT (0u) |
◆ SI1133_ADCCONFIG_DECIM_RATE_MASK
#define SI1133_ADCCONFIG_DECIM_RATE_MASK (0x60) |
◆ SI1133_ADCCONFIG_DECIM_RATE_SHIFT
#define SI1133_ADCCONFIG_DECIM_RATE_SHIFT (5u) |
◆ SI1133_ADCMUX_DEEP_UV
#define SI1133_ADCMUX_DEEP_UV (25u) |
◆ SI1133_ADCMUX_LARGE_IR
#define SI1133_ADCMUX_LARGE_IR (2u) |
◆ SI1133_ADCMUX_LARGE_WHITE
#define SI1133_ADCMUX_LARGE_WHITE (13u) |
◆ SI1133_ADCMUX_MEDIUM_IR
#define SI1133_ADCMUX_MEDIUM_IR (1u) |
◆ SI1133_ADCMUX_SMALL_IR
#define SI1133_ADCMUX_SMALL_IR (0u) |
◆ SI1133_ADCMUX_UV
#define SI1133_ADCMUX_UV (24u) |
◆ SI1133_ADCMUX_WHITE
#define SI1133_ADCMUX_WHITE (11u) |
◆ SI1133_ADCPOST_24BIT_OUT_MASK
#define SI1133_ADCPOST_24BIT_OUT_MASK (0x40) |
◆ SI1133_ADCPOST_POSTSHIFT_MASK
#define SI1133_ADCPOST_POSTSHIFT_MASK (0x38) |
◆ SI1133_ADCPOST_POSTSHIFT_SHIFT
#define SI1133_ADCPOST_POSTSHIFT_SHIFT (3u) |
◆ SI1133_ADCPOST_THRESH_SEL_MASK
#define SI1133_ADCPOST_THRESH_SEL_MASK (0x03) |
◆ SI1133_ADCPOST_THRESH_SEL_SHIFT
#define SI1133_ADCPOST_THRESH_SEL_SHIFT (0u) |
◆ SI1133_ADCSENS_HSIG_MASK
#define SI1133_ADCSENS_HSIG_MASK (0x80) |
◆ SI1133_ADCSENS_HW_GAIN_MASK
#define SI1133_ADCSENS_HW_GAIN_MASK (0x0f) |
◆ SI1133_ADCSENS_HW_GAIN_SHIFT
#define SI1133_ADCSENS_HW_GAIN_SHIFT (0u) |
◆ SI1133_ADCSENS_SW_GAIN_MASK
#define SI1133_ADCSENS_SW_GAIN_MASK (0x70) |
◆ SI1133_ADCSENS_SW_GAIN_SHIFT
#define SI1133_ADCSENS_SW_GAIN_SHIFT (4u) |
◆ SI1133_CMD_FORCE
#define SI1133_CMD_FORCE (0x11) |
◆ SI1133_CMD_PARAM_QUERY
#define SI1133_CMD_PARAM_QUERY (0x40) /* Add to SI1133_PARAM_* */ |
◆ SI1133_CMD_PARAM_SET
#define SI1133_CMD_PARAM_SET (0x80) /* Add to SI1133_PARAM_* */ |
◆ SI1133_CMD_PAUSE
#define SI1133_CMD_PAUSE (0x12) |
◆ SI1133_CMD_RESET_CMD_CTR
#define SI1133_CMD_RESET_CMD_CTR (0x00) |
◆ SI1133_CMD_RESET_SW
#define SI1133_CMD_RESET_SW (0x01) |
◆ SI1133_CMD_START
#define SI1133_CMD_START (0x13) |
◆ SI1133_I2C_ADDRESS
#define SI1133_I2C_ADDRESS (0x52) /* or 0x55 */ |
◆ SI1133_ID
◆ SI1133_MEASCONFIG_COUNTER_IDX_MASK
#define SI1133_MEASCONFIG_COUNTER_IDX_MASK (0xc0) |
◆ SI1133_MEASCONFIG_COUNTER_IDX_SHIFT
#define SI1133_MEASCONFIG_COUNTER_IDX_SHIFT (6u) |
◆ SI1133_NUM_CHANNELS
#define SI1133_NUM_CHANNELS (6u) |
◆ SI1133_PARAM_ADCCONFIG0
#define SI1133_PARAM_ADCCONFIG0 (0x02) |
◆ SI1133_PARAM_ADCCONFIG1
#define SI1133_PARAM_ADCCONFIG1 (0x06) |
◆ SI1133_PARAM_ADCCONFIG2
#define SI1133_PARAM_ADCCONFIG2 (0x0a) |
◆ SI1133_PARAM_ADCCONFIG3
#define SI1133_PARAM_ADCCONFIG3 (0x0e) |
◆ SI1133_PARAM_ADCCONFIG4
#define SI1133_PARAM_ADCCONFIG4 (0x12) |
◆ SI1133_PARAM_ADCCONFIG5
#define SI1133_PARAM_ADCCONFIG5 (0x16) |
◆ SI1133_PARAM_ADCPOST0
#define SI1133_PARAM_ADCPOST0 (0x04) |
◆ SI1133_PARAM_ADCPOST1
#define SI1133_PARAM_ADCPOST1 (0x08) |
◆ SI1133_PARAM_ADCPOST2
#define SI1133_PARAM_ADCPOST2 (0x0c) |
◆ SI1133_PARAM_ADCPOST3
#define SI1133_PARAM_ADCPOST3 (0x10) |
◆ SI1133_PARAM_ADCPOST4
#define SI1133_PARAM_ADCPOST4 (0x14) |
◆ SI1133_PARAM_ADCPOST5
#define SI1133_PARAM_ADCPOST5 (0x18) |
◆ SI1133_PARAM_ADCSENS0
#define SI1133_PARAM_ADCSENS0 (0x03) |
◆ SI1133_PARAM_ADCSENS1
#define SI1133_PARAM_ADCSENS1 (0x07) |
◆ SI1133_PARAM_ADCSENS2
#define SI1133_PARAM_ADCSENS2 (0x0b) |
◆ SI1133_PARAM_ADCSENS3
#define SI1133_PARAM_ADCSENS3 (0x0f) |
◆ SI1133_PARAM_ADCSENS4
#define SI1133_PARAM_ADCSENS4 (0x13) |
◆ SI1133_PARAM_ADCSENS5
#define SI1133_PARAM_ADCSENS5 (0x17) |
◆ SI1133_PARAM_BURST
#define SI1133_PARAM_BURST (0x2b) |
◆ SI1133_PARAM_CHAN_LIST
#define SI1133_PARAM_CHAN_LIST (0x01) |
◆ SI1133_PARAM_I2C_ADDR
#define SI1133_PARAM_I2C_ADDR (0x00) |
◆ SI1133_PARAM_MEASCONFIG0
#define SI1133_PARAM_MEASCONFIG0 (0x05) |
◆ SI1133_PARAM_MEASCONFIG1
#define SI1133_PARAM_MEASCONFIG1 (0x09) |
◆ SI1133_PARAM_MEASCONFIG2
#define SI1133_PARAM_MEASCONFIG2 (0x0d) |
◆ SI1133_PARAM_MEASCONFIG3
#define SI1133_PARAM_MEASCONFIG3 (0x11) |
◆ SI1133_PARAM_MEASCONFIG4
#define SI1133_PARAM_MEASCONFIG4 (0x15) |
◆ SI1133_PARAM_MEASCONFIG5
#define SI1133_PARAM_MEASCONFIG5 (0x19) |
◆ SI1133_PARAM_MEASCOUNT0
#define SI1133_PARAM_MEASCOUNT0 (0x1c) |
◆ SI1133_PARAM_MEASCOUNT1
#define SI1133_PARAM_MEASCOUNT1 (0x1d) |
◆ SI1133_PARAM_MEASCOUNT2
#define SI1133_PARAM_MEASCOUNT2 (0x1e) |
◆ SI1133_PARAM_MEASRATE_H
#define SI1133_PARAM_MEASRATE_H (0x1a) |
◆ SI1133_PARAM_MEASRATE_L
#define SI1133_PARAM_MEASRATE_L (0x1b) |
◆ SI1133_PARAM_THRESHOLD0_H
#define SI1133_PARAM_THRESHOLD0_H (0x25) |
◆ SI1133_PARAM_THRESHOLD0_L
#define SI1133_PARAM_THRESHOLD0_L (0x26) |
◆ SI1133_PARAM_THRESHOLD1_H
#define SI1133_PARAM_THRESHOLD1_H (0x27) |
◆ SI1133_PARAM_THRESHOLD1_L
#define SI1133_PARAM_THRESHOLD1_L (0x28) |
◆ SI1133_PARAM_THRESHOLD2_H
#define SI1133_PARAM_THRESHOLD2_H (0x29) |
◆ SI1133_PARAM_THRESHOLD2_L
#define SI1133_PARAM_THRESHOLD2_L (0x2a) |
◆ SI1133_REG_COMMAND
#define SI1133_REG_COMMAND (0x0b) |
◆ SI1133_REG_HOSTIN0
#define SI1133_REG_HOSTIN0 (0x0a) |
◆ SI1133_REG_HOSTOUTx
#define SI1133_REG_HOSTOUTx (0x13) /* Ranges from 0x13 to 0x2c */ |
◆ SI1133_REG_HW_ID
#define SI1133_REG_HW_ID (0x01) |
◆ SI1133_REG_INFO0
#define SI1133_REG_INFO0 (0x03) |
◆ SI1133_REG_INFO1
#define SI1133_REG_INFO1 (0x04) |
◆ SI1133_REG_IRQ_STATUS
#define SI1133_REG_IRQ_STATUS (0x12) |
◆ SI1133_REG_IRQENABLE
#define SI1133_REG_IRQENABLE (0x0f) /* Also RESET in the datasheet.*/ |
◆ SI1133_REG_PART_ID
#define SI1133_REG_PART_ID (0x00) |
◆ SI1133_REG_RESPONSE0
#define SI1133_REG_RESPONSE0 (0x11) |
◆ SI1133_REG_RESPONSE1
#define SI1133_REG_RESPONSE1 (0x10) |
◆ SI1133_REG_REV_ID
#define SI1133_REG_REV_ID (0x02) |
◆ SI1133_RESP0_CMD_ERR_MASK
#define SI1133_RESP0_CMD_ERR_MASK (0x10) |
◆ SI1133_RESP0_COUNTER_MASK
#define SI1133_RESP0_COUNTER_MASK (0x0f) |
◆ SI1133_RESP0_ERR_ADC_OVERFLOW
#define SI1133_RESP0_ERR_ADC_OVERFLOW (0x88) |
◆ SI1133_RESP0_ERR_BUFFER_OVERFLOW
#define SI1133_RESP0_ERR_BUFFER_OVERFLOW (0x89) |
◆ SI1133_RESP0_ERR_INVALID_COMMAND
#define SI1133_RESP0_ERR_INVALID_COMMAND (0x01) |
◆ SI1133_RESP0_ERR_INVALID_PARAM_ADDR
#define SI1133_RESP0_ERR_INVALID_PARAM_ADDR (0x80) |
◆ SI1133_RESP0_RUNNING_MASK
#define SI1133_RESP0_RUNNING_MASK (0x80) |
◆ SI1133_RESP0_SLEEP_MASK
#define SI1133_RESP0_SLEEP_MASK (0x20) |
◆ SI1133_RESP0_SUSPEND_MASK
#define SI1133_RESP0_SUSPEND_MASK (0x40) |
◆ SI1133_STARTUP_TIME_MS
#define SI1133_STARTUP_TIME_MS (25u) |
◆ si1133_channel_params_t
Si1133 channel parameters.
These parameters define how a "channel" is sampled, ADC settings, resolution timing, etc. These four register values define a single channel. This is a convenience struct to handle them together in the same order as they appear in the parameter list below.