xh3irq.h interrupt controller support More...

Detailed Description

xh3irq.h interrupt controller support

Author: Tom Hert git@a.nosp@m.nnsa.nosp@m.nn.eu

Definition in file xh3irq.h.

#include <stdio.h>
#include "panic.h"
#include "cpu_conf.h"

Include dependency graph for xh3irq.h:

#define	MEIP_OFFSET 11
	Hazard3 has internal registers to individually filter which external IRQs appear in meip.

#define	MEIP_MASK 0x1
	Mask to extract the MEIP bit from MIP/MISE.

#define	MEINEXT_IRQ_OFFSET 2
	Index of the highest-priority active external interrupt.

#define	MEINEXT_MASK 0x1FF
	Mask to extract the IRQ number from MEINEXT.

#define	INTERRUPT_ARRAY_MASK_OFFSET 16
	XH3IRQ Interrupt arrays have a window to access the IRQ bits.

const void *	vector_cpu [CPU_IRQ_NUMOF]
	CPU specific interrupt vector table.

uint32_t	xh3irq_has_pending (void)
	Check if there are any pending interrupts.

void	xh3irq_handler (void)
	The main IRQ handler, called from the assembly IRQ handler.

void	xh3irq_enable_irq (uint32_t irq_no)
	Enable the given IRQ number.

void	xh3irq_disable_irq (uint32_t irq_no)
	Disable the given IRQ number.

void	xh3irq_force_irq (uint32_t irq_no)
	Force the given IRQ number to be pending.

Macro Definition Documentation

◆ INTERRUPT_ARRAY_MASK_OFFSET

#define INTERRUPT_ARRAY_MASK_OFFSET 16

XH3IRQ Interrupt arrays have a window to access the IRQ bits.

Definition at line 53 of file xh3irq.h.

◆ MEINEXT_IRQ_OFFSET

#define MEINEXT_IRQ_OFFSET 2

Index of the highest-priority active external interrupt.

Zero when no external interrupts with sufficient priority are both pending and enabled

Definition at line 49 of file xh3irq.h.

◆ MEINEXT_MASK

#define MEINEXT_MASK 0x1FF

Mask to extract the IRQ number from MEINEXT.

Definition at line 51 of file xh3irq.h.

◆ MEIP_MASK

#define MEIP_MASK 0x1

Mask to extract the MEIP bit from MIP/MISE.

Definition at line 43 of file xh3irq.h.

◆ MEIP_OFFSET

#define MEIP_OFFSET 11

Hazard3 has internal registers to individually filter which external IRQs appear in meip.

When meip is 1, this indicates there is at least one external interrupt which is asserted (hence pending in mieipa), enabled in meiea, and of priority greater than or equal to the current preemption level in meicontext.preempt.

Definition at line 41 of file xh3irq.h.

Function Documentation

◆ xh3irq_disable_irq()

void xh3irq_disable_irq ( uint32_t irq_no )

Disable the given IRQ number.

Parameters

irq_no The IRQ number to disable

◆ xh3irq_enable_irq()

void xh3irq_enable_irq ( uint32_t irq_no )

Enable the given IRQ number.

Parameters

irq_no The IRQ number to enable

◆ xh3irq_force_irq()

void xh3irq_force_irq ( uint32_t irq_no )

Force the given IRQ number to be pending.

Parameters

irq_no The IRQ number to force

Note: The IRQ still must be enabled to be handled

◆ xh3irq_handler()

void xh3irq_handler ( void )

The main IRQ handler, called from the assembly IRQ handler.

Note: This function must clear the pending interrupt in the interrupt controller

◆ xh3irq_has_pending()

uint32_t xh3irq_has_pending ( void )

Check if there are any pending interrupts.

Return values

1	if there are pending interrupts
0	otherwise

Variable Documentation

◆ vector_cpu

const void* vector_cpu[CPU_IRQ_NUMOF]

extern

CPU specific interrupt vector table.

See also: 3.2 Interrupts and IRQn_Type in RP2350.h