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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2020 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "periph_cpu.h"
20#include "cfg_clock_32_0.h"
21#include "cfg_rtt_default.h"
22#include "cfg_timer_default.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
35static const uart_conf_t uart_config[] = {
36 {
37 .dev = NRF_UARTE0,
38 .rx_pin = GPIO_PIN(0, 4),
39 .tx_pin = GPIO_PIN(0, 5),
40#ifdef MODULE_PERIPH_UART_HW_FC
41 .rts_pin = GPIO_UNDEF,
42 .cts_pin = GPIO_UNDEF,
43#endif
44 .irqn = UARTE0_UART0_IRQn,
45 },
46};
47
51#define UART_0_ISR (isr_uart0)
55#define UART_NUMOF ARRAY_SIZE(uart_config)
57
65static const i2c_conf_t i2c_config[] = {
66 { /* External connectors */
67 .dev = NRF_TWIM0,
68 .scl = GPIO_PIN(0, 0), /* D19 */
69 .sda = GPIO_PIN(0, 30), /* D20 */
70 .speed = I2C_SPEED_NORMAL
71 },
72 { /* On board sensors */
73 .dev = NRF_TWIM1,
74 .scl = GPIO_PIN(0, 25),
75 .sda = GPIO_PIN(0, 24),
76 .speed = I2C_SPEED_NORMAL
77 },
78};
79
83#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
85
93static const spi_conf_t spi_config[] = {
94 { /* External connectors */
95 .dev = NRF_SPIM0,
96 .sclk = GPIO_PIN(0, 23), /* D13 */
97 .mosi = GPIO_PIN(0, 21), /* D15 */
98 .miso = GPIO_PIN(0, 22), /* D14 */
99 },
100 { /* TFT LCD screen */
101 .dev = NRF_SPIM1,
102 .sclk = GPIO_PIN(0, 14),
103 .mosi = GPIO_PIN(0, 15),
104 .miso = GPIO_PIN(0, 0),
105 },
106};
107
111#define SPI_NUMOF ARRAY_SIZE(spi_config)
113
114#ifdef __cplusplus
115}
116#endif
117
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
Common clock configuration for the nRF52 based boards.
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217