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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2021 ML!PA Consulting GmbH
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
28#ifndef CLOCK_CORECLOCK
29#define CLOCK_CORECLOCK MHZ(120)
30#endif
32
37#define EXTERNAL_OSC32_SOURCE 0
38#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 1
40
45#define USE_VREG_BUCK (1)
46
51static const tc32_conf_t timer_config[] = {
52 { /* Timer 0 - System Clock */
53 .dev = TC0,
54 .irq = TC0_IRQn,
55 .mclk = &MCLK->APBAMASK.reg,
56 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
57 .gclk_id = TC0_GCLK_ID,
58 .gclk_src = SAM0_GCLK_TIMER,
59 .flags = TC_CTRLA_MODE_COUNT32,
60 },
61 { /* Timer 1 */
62 .dev = TC2,
63 .irq = TC2_IRQn,
64 .mclk = &MCLK->APBBMASK.reg,
65 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
66 .gclk_id = TC2_GCLK_ID,
67 .gclk_src = SAM0_GCLK_TIMER,
68 .flags = TC_CTRLA_MODE_COUNT32,
69 }
70};
71
72/* Timer 0 configuration */
73#define TIMER_0_CHANNELS 2
74#define TIMER_0_ISR isr_tc0
75
76/* Timer 1 configuration */
77#define TIMER_1_CHANNELS 2
78#define TIMER_1_ISR isr_tc2
79
80#define TIMER_NUMOF ARRAY_SIZE(timer_config)
82
87static const uart_conf_t uart_config[] = {
88 {
89 .dev = &SERCOM3->USART,
90 .rx_pin = GPIO_PIN(PA, 16),
91 .tx_pin = GPIO_PIN(PA, 17),
92#ifdef MODULE_PERIPH_UART_HW_FC
93 .rts_pin = GPIO_UNDEF,
94 .cts_pin = GPIO_UNDEF,
95#endif
96 .mux = GPIO_MUX_D,
97 .rx_pad = UART_PAD_RX_1,
98 .tx_pad = UART_PAD_TX_0,
99 .flags = UART_FLAG_NONE,
100 .gclk_src = SAM0_GCLK_PERIPH,
101 },
102};
103
104/* interrupt function name mapping */
105#define UART_0_ISR isr_sercom3_2
106#define UART_0_ISR_TX isr_sercom3_0
107
108#define UART_NUMOF ARRAY_SIZE(uart_config)
110
115#define PWM_0_EN 1
116
117#if PWM_0_EN
118/* PWM0 channels */
119static const pwm_conf_chan_t pwm_chan0_config[] = {
120 /* GPIO pin, MUX value, TCC channel */
121 { GPIO_PIN(PA, 22), GPIO_MUX_G, 2 },
122};
123#endif
124
125/* PWM device configuration */
126static const pwm_conf_t pwm_config[] = {
127#if PWM_0_EN
128 { .tim = TCC_CONFIG(TCC0),
129 .chan = pwm_chan0_config,
130 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
131 .gclk_src = SAM0_GCLK_PERIPH,
132 },
133#endif
134};
135
136/* number of devices that are actually defined */
137#define PWM_NUMOF ARRAY_SIZE(pwm_config)
139
144static const spi_conf_t spi_config[] = {
145 {
146 .dev = &(SERCOM1->SPI),
147 .miso_pin = GPIO_PIN(PB, 23),
148 .mosi_pin = GPIO_PIN(PA, 0),
149 .clk_pin = GPIO_PIN(PA, 1),
150 .miso_mux = GPIO_MUX_C,
151 .mosi_mux = GPIO_MUX_D,
152 .clk_mux = GPIO_MUX_D,
153 .miso_pad = SPI_PAD_MISO_3,
154 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
155 .gclk_src = SAM0_GCLK_PERIPH,
156#ifdef MODULE_PERIPH_DMA
157 .tx_trigger = SERCOM1_DMAC_ID_TX,
158 .rx_trigger = SERCOM1_DMAC_ID_RX,
159#endif
160 },
161#ifdef MODULE_PERIPH_SPI_ON_QSPI
162 { /* QSPI in SPI mode */
163 .dev = QSPI,
164 .miso_pin = SAM0_QSPI_PIN_DATA_1,
165 .mosi_pin = SAM0_QSPI_PIN_DATA_0,
166 .clk_pin = SAM0_QSPI_PIN_CLK,
167 .miso_mux = SAM0_QSPI_MUX,
168 .mosi_mux = SAM0_QSPI_MUX,
169 .clk_mux = SAM0_QSPI_MUX,
170 .miso_pad = SPI_PAD_MISO_0, /* unused */
171 .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
172 .gclk_src = SAM0_GCLK_MAIN, /* unused */
173#ifdef MODULE_PERIPH_DMA
174 .tx_trigger = QSPI_DMAC_ID_TX,
175 .rx_trigger = QSPI_DMAC_ID_RX,
176#endif
177 },
178#endif
179};
180
181#define SPI_NUMOF ARRAY_SIZE(spi_config)
183
188static const i2c_conf_t i2c_config[] = {
189 {
190 .dev = &(SERCOM2->I2CM),
191 .speed = I2C_SPEED_NORMAL,
192 .scl_pin = GPIO_PIN(PA, 12),
193 .sda_pin = GPIO_PIN(PA, 13),
194 .mux = GPIO_MUX_C,
195 .gclk_src = SAM0_GCLK_PERIPH,
196 .flags = I2C_FLAG_NONE
197 },
198};
199
200#define I2C_NUMOF ARRAY_SIZE(i2c_config)
202
207#ifndef RTT_FREQUENCY
208#define RTT_FREQUENCY (32768U)
209#endif
211
216static const sam0_common_usb_config_t sam_usbdev_config[] = {
217 {
218 .dm = GPIO_PIN(PA, 24),
219 .dp = GPIO_PIN(PA, 25),
220 .d_mux = GPIO_MUX_H,
221 .device = &USB->DEVICE,
222 .gclk_src = SAM0_GCLK_PERIPH,
223 }
224};
226
231
232/* ADC Default values */
233#define ADC_GCLK_SRC SAM0_GCLK_PERIPH
234#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
235
236#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
237#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
238
239static const adc_conf_chan_t adc_channels[] = {
240 /* port, pin, muxpos, dev */
241 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 },
242 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 },
243 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 },
244 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 },
245 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 },
246 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 },
247};
248
249#define ADC_NUMOF ARRAY_SIZE(adc_channels)
251
256 /* Must not exceed 12 MHz */
257#define DAC_CLOCK SAM0_GCLK_TIMER
258 /* Use external reference voltage on PA03 */
259 /* (You have to manually connect PA03 with Vcc) */
260 /* Internal reference only gives 1V */
261#define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
263
264#ifdef __cplusplus
265}
266#endif
267
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:82
@ UART_PAD_RX_1
select pad 1
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PA
port A
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition periph_cpu.h:129
#define SAM0_QSPI_PIN_CLK
Clock.
Definition periph_cpu.h:268
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition periph_cpu.h:130
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI.
Definition periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO.
Definition periph_cpu.h:271
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition periph_cpu.h:127
#define SAM0_QSPI_MUX
QSPI mux.
Definition periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition periph_cpu.h:128
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition periph_cpu.h:131
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:78
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:125
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:81
ADC Channel Configuration.
I2C configuration structure.
Definition periph_cpu.h:298
PWM channel configuration data structure.
PWM device configuration.
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
UART device configuration.
Definition periph_cpu.h:217