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periph_conf.h
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1/*
2 * Copyright (C) 2020 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22#include "periph_cpu.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
32#ifndef CLOCK_CORECLOCK
33#define CLOCK_CORECLOCK MHZ(120)
34#endif
41#define EXTERNAL_OSC32_SOURCE 0
42#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 1
49#define USE_VREG_BUCK (1)
50
55static const tc32_conf_t timer_config[] = {
56 { /* Timer 0 - System Clock */
57 .dev = TC0,
58 .irq = TC0_IRQn,
59 .mclk = &MCLK->APBAMASK.reg,
60 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
61 .gclk_id = TC0_GCLK_ID,
62 .gclk_src = SAM0_GCLK_TIMER,
63 .flags = TC_CTRLA_MODE_COUNT32,
64 },
65 { /* Timer 1 */
66 .dev = TC2,
67 .irq = TC2_IRQn,
68 .mclk = &MCLK->APBBMASK.reg,
69 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
70 .gclk_id = TC2_GCLK_ID,
71 .gclk_src = SAM0_GCLK_TIMER,
72 .flags = TC_CTRLA_MODE_COUNT32,
73 }
74};
75
76/* Timer 0 configuration */
77#define TIMER_0_CHANNELS 2
78#define TIMER_0_ISR isr_tc0
79
80/* Timer 1 configuration */
81#define TIMER_1_CHANNELS 2
82#define TIMER_1_ISR isr_tc2
83
84#define TIMER_NUMOF ARRAY_SIZE(timer_config)
91static const uart_conf_t uart_config[] = {
92 { /* Virtual COM Port */
93 .dev = &SERCOM5->USART,
94 .rx_pin = GPIO_PIN(PB, 16),
95 .tx_pin = GPIO_PIN(PB, 17),
96#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
97 .rts_pin = GPIO_UNDEF,
98 .cts_pin = GPIO_UNDEF,
99#endif
100 .mux = GPIO_MUX_C,
101 .rx_pad = UART_PAD_RX_1,
102 .tx_pad = UART_PAD_TX_0,
103 .flags = UART_FLAG_NONE,
104 .gclk_src = SAM0_GCLK_PERIPH,
105 }
106};
107
108/* interrupt function name mapping */
109#define UART_0_ISR isr_sercom5_2
110#define UART_0_ISR_TX isr_sercom5_0
111
112#define UART_NUMOF ARRAY_SIZE(uart_config)
119#define PWM_0_EN 1
120
121#if PWM_0_EN
122/* PWM0 channels */
123static const pwm_conf_chan_t pwm_chan0_config[] = {
124 /* GPIO pin, MUX value, TCC channel */
125 { GPIO_PIN(PA, 22), GPIO_MUX_G, 2 },
126};
127#endif
128
129/* PWM device configuration */
130static const pwm_conf_t pwm_config[] = {
131#if PWM_0_EN
132 { .tim = TCC_CONFIG(TCC0),
133 .chan = pwm_chan0_config,
134 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
135 .gclk_src = SAM0_GCLK_PERIPH,
136 },
137#endif
138};
139
140/* number of devices that are actually defined */
141#define PWM_NUMOF ARRAY_SIZE(pwm_config)
148static const spi_conf_t spi_config[] = {
149 {
150 .dev = &(SERCOM1->SPI),
151 .miso_pin = GPIO_PIN(PB, 22),
152 .mosi_pin = GPIO_PIN(PB, 23),
153 .clk_pin = GPIO_PIN(PA, 17),
154 .miso_mux = GPIO_MUX_C,
155 .mosi_mux = GPIO_MUX_C,
156 .clk_mux = GPIO_MUX_C,
157 .miso_pad = SPI_PAD_MISO_2,
158 .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
159 .gclk_src = SAM0_GCLK_PERIPH,
160#ifdef MODULE_PERIPH_DMA
161 .tx_trigger = SERCOM1_DMAC_ID_TX,
162 .rx_trigger = SERCOM1_DMAC_ID_RX,
163#endif
164 },
165 { /* Connected to TFT display */
166 .dev = &(SERCOM4->SPI),
167 .miso_pin = GPIO_PIN(PB, 12),
168 .mosi_pin = GPIO_PIN(PB, 15),
169 .clk_pin = GPIO_PIN(PB, 13),
170 .miso_mux = GPIO_MUX_C,
171 .mosi_mux = GPIO_MUX_C,
172 .clk_mux = GPIO_MUX_C,
173 .miso_pad = SPI_PAD_MISO_0,
174 .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
175 .gclk_src = SAM0_GCLK_PERIPH,
176#ifdef MODULE_PERIPH_DMA
177 .tx_trigger = SERCOM4_DMAC_ID_TX,
178 .rx_trigger = SERCOM4_DMAC_ID_RX,
179#endif
180 },
181 { /* Connected to PDM Mic */
182 .dev = &(SERCOM3->SPI),
183 .miso_pin = GPIO_PIN(PA, 18),
184 .mosi_pin = GPIO_PIN(PA, 19),
185 .clk_pin = GPIO_PIN(PA, 16),
186 .miso_mux = GPIO_MUX_D,
187 .mosi_mux = GPIO_MUX_D,
188 .clk_mux = GPIO_MUX_D,
189 .miso_pad = SPI_PAD_MISO_2,
190 .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
191 .gclk_src = SAM0_GCLK_PERIPH,
192#ifdef MODULE_PERIPH_DMA
193 .tx_trigger = SERCOM4_DMAC_ID_TX,
194 .rx_trigger = SERCOM4_DMAC_ID_RX,
195#endif
196 },
197#ifdef MODULE_PERIPH_SPI_ON_QSPI
198 { /* QSPI in SPI mode */
199 .dev = QSPI,
200 .miso_pin = SAM0_QSPI_PIN_DATA_1,
201 .mosi_pin = SAM0_QSPI_PIN_DATA_0,
202 .clk_pin = SAM0_QSPI_PIN_CLK,
203 .miso_mux = SAM0_QSPI_MUX,
204 .mosi_mux = SAM0_QSPI_MUX,
205 .clk_mux = SAM0_QSPI_MUX,
206 .miso_pad = SPI_PAD_MISO_0, /* unused */
207 .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
208 .gclk_src = SAM0_GCLK_MAIN, /* unused */
209#ifdef MODULE_PERIPH_DMA
210 .tx_trigger = QSPI_DMAC_ID_TX,
211 .rx_trigger = QSPI_DMAC_ID_RX,
212#endif
213 },
214#endif
215};
216
217#define SPI_NUMOF ARRAY_SIZE(spi_config)
224static const i2c_conf_t i2c_config[] = {
225 {
226 .dev = &(SERCOM2->I2CM),
227 .speed = I2C_SPEED_NORMAL,
228 .scl_pin = GPIO_PIN(PA, 13),
229 .sda_pin = GPIO_PIN(PA, 12),
230 .mux = GPIO_MUX_C,
231 .gclk_src = SAM0_GCLK_PERIPH,
232 .flags = I2C_FLAG_NONE
233 },
234};
235#define I2C_NUMOF ARRAY_SIZE(i2c_config)
242#ifndef RTT_FREQUENCY
243#define RTT_FREQUENCY (32768U)
244#endif
251static const sam0_common_usb_config_t sam_usbdev_config[] = {
252 {
253 .dm = GPIO_PIN(PA, 24),
254 .dp = GPIO_PIN(PA, 25),
255 .d_mux = GPIO_MUX_H,
256 .device = &USB->DEVICE,
257 .gclk_src = SAM0_GCLK_48MHZ,
258 }
259};
267/* ADC Default values */
268#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV128
269
270#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
271#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
272
273static const adc_conf_chan_t adc_channels[] = {
274 /* port, pin, muxpos, dev */
275 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
276 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 }, /* A2 */
277 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 }, /* A3 */
278 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A4 */
279 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A5 */
280 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB01, .dev = ADC0 }, /* A6 - VMEAS */
281 { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB04, .dev = ADC1 }, /* A7 - Light sensor */
282};
283
284#define ADC_NUMOF ARRAY_SIZE(adc_channels)
291#define DAC_CLOCK SAM0_GCLK_TIMER
296#define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
299#ifdef __cplusplus
300}
301#endif
302
303#endif /* PERIPH_CONF_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:83
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:74
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition periph_cpu.h:130
#define SAM0_QSPI_PIN_CLK
Clock
Definition periph_cpu.h:269
#define ADC1_INPUTCTRL_MUXPOS_PB04
Alias for AIN6.
Definition periph_cpu.h:149
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition periph_cpu.h:131
#define ADC0_INPUTCTRL_MUXPOS_PB01
Alias for AIN13.
Definition periph_cpu.h:139
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition periph_cpu.h:271
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition periph_cpu.h:272
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition periph_cpu.h:128
#define SAM0_QSPI_MUX
QSPI mux
Definition periph_cpu.h:275
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition periph_cpu.h:129
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition periph_cpu.h:132
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:79
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:82
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM channel configuration data structure.
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Tc * dev
pointer to the used Timer device
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219