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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* Add specific clock configuration (HSE, LSE) for this board here */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23#include "periph_cpu.h"
24#include "clk_conf.h"
25#include "cfg_rtt_default.h"
26#include "cfg_timer_tim2.h"
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
36static const dma_conf_t dma_config[] = {
37 { .stream = 1 }, /* channel 2 */
38 { .stream = 2 }, /* channel 3 */
39 { .stream = 3 }, /* channel 4 */
40 { .stream = 4 }, /* channel 5 */
41 { .stream = 5 }, /* channel 6 */
42};
43
44#define DMA_SHARED_ISR_0 isr_dma1_channel2_3
45#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
46#define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7
47#define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */
48
49#define DMA_NUMOF ARRAY_SIZE(dma_config)
51
56static const uart_conf_t uart_config[] = {
57 {
58 .dev = USART1,
59 .rcc_mask = RCC_APB2ENR_USART1EN,
60 .rx_pin = GPIO_PIN(PORT_A, 10),
61 .tx_pin = GPIO_PIN(PORT_A, 9),
62 .rx_af = GPIO_AF4,
63 .tx_af = GPIO_AF4,
64 .bus = APB2,
65 .irqn = USART1_IRQn,
66 .type = STM32_USART,
67 .clk_src = 0, /* Use APB clock */
68#ifdef MODULE_PERIPH_DMA
69 .dma = 0,
70 .dma_chan = 3,
71#endif
72 },
73 {
74 .dev = USART2,
75 .rcc_mask = RCC_APB1ENR_USART2EN,
76 .rx_pin = GPIO_PIN(PORT_A, 3),
77 .tx_pin = GPIO_PIN(PORT_A, 2),
78 .rx_af = GPIO_AF4,
79 .tx_af = GPIO_AF4,
80 .bus = APB1,
81 .irqn = USART2_IRQn,
82 .type = STM32_USART,
83 .clk_src = 0, /* Use APB clock */
84#ifdef MODULE_PERIPH_DMA
85 .dma = 2,
86 .dma_chan = 4,
87#endif
88 },
89};
90
91#define UART_0_ISR (isr_usart1)
92#define UART_1_ISR (isr_usart2)
93
94#define UART_NUMOF ARRAY_SIZE(uart_config)
96
101static const spi_conf_t spi_config[] = {
102 {
103 .dev = SPI1, /* connected to SX1276 */
104 .mosi_pin = GPIO_PIN(PORT_A, 7),
105 .miso_pin = GPIO_PIN(PORT_A, 6),
106 .sclk_pin = GPIO_PIN(PORT_A, 5),
107 .cs_pin = SPI_CS_UNDEF,
108 .mosi_af = GPIO_AF0,
109 .miso_af = GPIO_AF0,
110 .sclk_af = GPIO_AF0,
111 .cs_af = GPIO_AF0,
112 .rccmask = RCC_APB2ENR_SPI1EN,
113 .apbbus = APB2,
114#ifdef MODULE_PERIPH_DMA
115 .tx_dma = 1,
116 .tx_dma_chan = 1,
117 .rx_dma = 0,
118 .rx_dma_chan = 1,
119#endif
120 },
121};
122
123#define SPI_NUMOF ARRAY_SIZE(spi_config)
125
130static const i2c_conf_t i2c_config[] = {
131 {
132 .dev = I2C1,
133 .speed = I2C_SPEED_NORMAL,
134 .scl_pin = GPIO_PIN(PORT_B, 6),
135 .sda_pin = GPIO_PIN(PORT_B, 7),
136 .scl_af = GPIO_AF4,
137 .sda_af = GPIO_AF4,
138 .bus = APB1,
139 .rcc_mask = RCC_APB1ENR_I2C1EN,
140 .irqn = I2C1_IRQn
141 }
142};
143
144#define I2C_0_ISR isr_i2c1
145
146#define I2C_NUMOF ARRAY_SIZE(i2c_config)
148
149#ifdef __cplusplus
150}
151#endif
152
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
DMA configuration.
Definition cpu_dma.h:31
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217