Configuration of CPU peripherals for STM32 Nucleo-G031K8 board.
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Configuration of CPU peripherals for STM32 Nucleo-G031K8 board.
- Author
- Hudson C. Dalpra dalpr.nosp@m.a.hc.nosp@m.d@gma.nosp@m.il.c.nosp@m.om
Definition in file periph_conf.h.
#include "periph_cpu.h"
#include "clk_conf.h"
Go to the source code of this file.
◆ SPI_NUMOF
◆ TIMER_0_ISR
| #define TIMER_0_ISR isr_tim3 |
◆ TIMER_NUMOF
◆ UART_0_ISR
| #define UART_0_ISR (isr_usart2) |
◆ UART_1_ISR
| #define UART_1_ISR (isr_usart1) |
◆ UART_NUMOF
◆ spi_config
Initial value:= {
{
.dev = SPI1,
.rccmask = RCC_APBENR2_SPI1EN,
.apbbus = APB12,
},
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ GPIO_AF0
use alternate function 0
Definition at line 81 of file periph_conf.h.
◆ timer_config
Initial value:= {
{
.dev = TIM3,
.max = 0x0000ffff,
.rcc_mask = RCC_APBENR1_TIM3EN,
.irqn = TIM3_IRQn
}
}
@ APB1
Advanced Peripheral Bus 1.
Definition at line 29 of file periph_conf.h.
◆ uart_config
Initial value:= {
{
.dev = USART2,
.rcc_mask = RCC_APBENR1_USART2EN,
.irqn = USART2_IRQn,
},
{
.dev = USART1,
.rcc_mask = RCC_APBENR2_USART1EN,
.bus = APB12,
.irqn = USART1_IRQn,
}
}
@ GPIO_AF1
use alternate function 1
Definition at line 48 of file periph_conf.h.