Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2019 ML!PA Consulting GmbH
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
18
19#include "periph_cpu.h"
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
31#ifndef USE_XOSC_ONLY
32#define USE_XOSC_ONLY (0)
33#endif
34
39#define XOSC1_FREQUENCY MHZ(12)
41
46#ifndef CLOCK_CORECLOCK
47#if USE_XOSC_ONLY
48#define CLOCK_CORECLOCK XOSC1_FREQUENCY
49#else
50#define CLOCK_CORECLOCK MHZ(120)
51#endif
52#endif
54
59#define EXTERNAL_OSC32_SOURCE 1
60#define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
62
67#define USE_VREG_BUCK (1)
68
73static const tc32_conf_t timer_config[] = {
74 { /* Timer 0 - System Clock */
75 .dev = TC0,
76 .irq = TC0_IRQn,
77 .mclk = &MCLK->APBAMASK.reg,
78 .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
79 .gclk_id = TC0_GCLK_ID,
80 .gclk_src = SAM0_GCLK_TIMER,
81 .flags = TC_CTRLA_MODE_COUNT32,
82 },
83 { /* Timer 1 */
84 .dev = TC2,
85 .irq = TC2_IRQn,
86 .mclk = &MCLK->APBBMASK.reg,
87 .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
88 .gclk_id = TC2_GCLK_ID,
89 .gclk_src = SAM0_GCLK_TIMER,
90 .flags = TC_CTRLA_MODE_COUNT32,
91 }
92};
93
94/* Timer 0 configuration */
95#define TIMER_0_CHANNELS 2
96#define TIMER_0_ISR isr_tc0
97
98/* Timer 1 configuration */
99#define TIMER_1_CHANNELS 2
100#define TIMER_1_ISR isr_tc2
101
102#define TIMER_NUMOF ARRAY_SIZE(timer_config)
104
109#define AT6561_STBY_PIN GPIO_PIN(PC, 13)
111
117static const can_conf_t candev_conf[] = {
118 {
119 .can = CAN1,
120 .rx_pin = GPIO_PIN(PB, 13),
121 .tx_pin = GPIO_PIN(PB, 12),
122 .gclk_src = SAM0_GCLK_PERIPH,
123 .enable_pin = AT6561_STBY_PIN,
124 .enable_pin_mode = GPIO_OUT,
125 .enable_pin_active_low = true,
126 }
127};
128
130#define ISR_CAN1 isr_can1
131
133#define CAN_NUMOF ARRAY_SIZE(candev_conf)
135
140static const uart_conf_t uart_config[] = {
141 { /* Virtual COM Port */
142 .dev = &SERCOM2->USART,
143 .rx_pin = GPIO_PIN(PB, 24),
144 .tx_pin = GPIO_PIN(PB, 25),
145 .mux = GPIO_MUX_D,
146 .rx_pad = UART_PAD_RX_1,
147 .tx_pad = UART_PAD_TX_0,
148 .flags = UART_FLAG_NONE,
149 .gclk_src = SAM0_GCLK_PERIPH,
150 },
151 { /* EXT1 */
152 .dev = &SERCOM0->USART,
153 .rx_pin = GPIO_PIN(PA, 5),
154 .tx_pin = GPIO_PIN(PA, 4),
155#ifdef MODULE_PERIPH_UART_HW_FC
156 .rts_pin = GPIO_PIN(PA, 6),
157 .cts_pin = GPIO_PIN(PA, 7),
158#endif
159 .mux = GPIO_MUX_D,
160 .rx_pad = UART_PAD_RX_1,
161#ifdef MODULE_PERIPH_UART_HW_FC
163#else
164 .tx_pad = UART_PAD_TX_0,
165#endif
166 .flags = UART_FLAG_NONE,
167 .gclk_src = SAM0_GCLK_PERIPH,
168 },
169 { /* EXT2 */
170 .dev = &SERCOM5->USART,
171 .rx_pin = GPIO_PIN(PB, 17),
172 .tx_pin = GPIO_PIN(PB, 16),
173 .mux = GPIO_MUX_C,
174 .rx_pad = UART_PAD_RX_1,
175 .tx_pad = UART_PAD_TX_0,
176 .flags = UART_FLAG_NONE,
177 .gclk_src = SAM0_GCLK_PERIPH,
178 },
179 { /* EXT3 */
180 .dev = &SERCOM1->USART,
181 .rx_pin = GPIO_PIN(PC, 23),
182 .tx_pin = GPIO_PIN(PC, 22),
183 .mux = GPIO_MUX_C,
184 .rx_pad = UART_PAD_RX_1,
185 .tx_pad = UART_PAD_TX_0,
186 .flags = UART_FLAG_NONE,
187 .gclk_src = SAM0_GCLK_PERIPH,
188 }
189};
190
191/* interrupt function name mapping */
192#define UART_0_ISR isr_sercom2_2
193#define UART_0_ISR_TX isr_sercom2_0
194
195#define UART_1_ISR isr_sercom0_2
196#define UART_1_ISR_TX isr_sercom0_0
197
198#define UART_2_ISR isr_sercom5_2
199#define UART_2_ISR_TX isr_sercom5_0
200
201#define UART_3_ISR isr_sercom1_2
202#define UART_3_ISR_TX isr_sercom1_0
203
204#define UART_NUMOF ARRAY_SIZE(uart_config)
206
211
212/* PWM0 channels */
213static const pwm_conf_chan_t pwm_chan0_config[] = {
214 /* GPIO pin, MUX value, TCC channel */
215 {
216 .pin = GPIO_PIN(PC, 18),
217 .mux = GPIO_MUX_F,
218 .chan = 2
219 },
220};
221
222/* PWM device configuration */
223static const pwm_conf_t pwm_config[] = {
224 {
225 .tim = TCC_CONFIG(TCC0),
226 .chan = pwm_chan0_config,
227 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
228 .gclk_src = SAM0_GCLK_48MHZ,
229 },
230};
231
232/* number of devices that are actually defined */
233#define PWM_NUMOF ARRAY_SIZE(pwm_config)
235
240static const spi_conf_t spi_config[] = {
241 { /* EXT1 */
242 .dev = &(SERCOM4->SPI),
243 .miso_pin = GPIO_PIN(PB, 29),
244 .mosi_pin = GPIO_PIN(PB, 27),
245 .clk_pin = GPIO_PIN(PB, 26),
246 .miso_mux = GPIO_MUX_D,
247 .mosi_mux = GPIO_MUX_D,
248 .clk_mux = GPIO_MUX_D,
249 .miso_pad = SPI_PAD_MISO_3,
250 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
251 .gclk_src = SAM0_GCLK_PERIPH,
252#ifdef MODULE_PERIPH_DMA
253 .tx_trigger = SERCOM4_DMAC_ID_TX,
254 .rx_trigger = SERCOM4_DMAC_ID_RX,
255#endif
256
257 },
258 { /* EXT2, EXT3 */
259 .dev = &(SERCOM6->SPI),
260 .miso_pin = GPIO_PIN(PC, 7),
261 .mosi_pin = GPIO_PIN(PC, 4),
262 .clk_pin = GPIO_PIN(PC, 5),
263 .miso_mux = GPIO_MUX_C,
264 .mosi_mux = GPIO_MUX_C,
265 .clk_mux = GPIO_MUX_C,
266 .miso_pad = SPI_PAD_MISO_3,
267 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
268 .gclk_src = SAM0_GCLK_48MHZ,
269#ifdef MODULE_PERIPH_DMA
270 .tx_trigger = SERCOM6_DMAC_ID_TX,
271 .rx_trigger = SERCOM6_DMAC_ID_RX,
272#endif
273 },
274#ifdef MODULE_PERIPH_SPI_ON_QSPI
275 { /* QSPI in SPI mode */
276 .dev = QSPI,
277 .miso_pin = SAM0_QSPI_PIN_DATA_1,
278 .mosi_pin = SAM0_QSPI_PIN_DATA_0,
279 .clk_pin = SAM0_QSPI_PIN_CLK,
280 .miso_mux = SAM0_QSPI_MUX,
281 .mosi_mux = SAM0_QSPI_MUX,
282 .clk_mux = SAM0_QSPI_MUX,
283 .miso_pad = SPI_PAD_MISO_0, /* unused */
284 .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
285 .gclk_src = SAM0_GCLK_MAIN, /* unused */
286#ifdef MODULE_PERIPH_DMA
287 .tx_trigger = QSPI_DMAC_ID_TX,
288 .rx_trigger = QSPI_DMAC_ID_RX,
289#endif
290 },
291#endif
292};
293
294#define SPI_NUMOF ARRAY_SIZE(spi_config)
296
301static const i2c_conf_t i2c_config[] = {
302 { /* EXT1 */
303 .dev = &(SERCOM3->I2CM),
304 .speed = I2C_SPEED_NORMAL,
305 .scl_pin = GPIO_PIN(PA, 23),
306 .sda_pin = GPIO_PIN(PA, 22),
307 .mux = GPIO_MUX_C,
308 .gclk_src = SAM0_GCLK_PERIPH,
309 .flags = I2C_FLAG_NONE
310 },
311 { /* EXT2, EXT3 */
312 .dev = &(SERCOM7->I2CM),
313 .speed = I2C_SPEED_NORMAL,
314 .scl_pin = GPIO_PIN(PD, 9),
315 .sda_pin = GPIO_PIN(PD, 8),
316 .mux = GPIO_MUX_C,
317 .gclk_src = SAM0_GCLK_PERIPH,
318 .flags = I2C_FLAG_NONE
319 }
320};
321
322#define I2C_NUMOF ARRAY_SIZE(i2c_config)
324
329#ifndef RTT_FREQUENCY
330#define RTT_FREQUENCY (32768U)
331#endif
333
338static const sam0_common_usb_config_t sam_usbdev_config[] = {
339 {
340 .dm = GPIO_PIN(PA, 24),
341 .dp = GPIO_PIN(PA, 25),
342 .d_mux = GPIO_MUX_H,
343 .device = &USB->DEVICE,
344 .gclk_src = SAM0_GCLK_PERIPH,
345 }
346};
348
353
354/* ADC Default values */
355#define ADC_GCLK_SRC SAM0_GCLK_PERIPH
356#define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
357
358#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
359#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
360
361static const adc_conf_chan_t adc_channels[] = {
362 /* port, pin, muxpos, dev */
363 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA03, .dev = ADC0 },
364 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 },
365 { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA07, .dev = ADC0 }
366};
367
368#define ADC_NUMOF ARRAY_SIZE(adc_channels)
370
375 /* Must not exceed 12 MHz */
376#define DAC_CLOCK SAM0_GCLK_TIMER
377#ifndef DAC_VREF
378 /* Internal reference only gives 1V */
379#define DAC_VREF DAC_CTRLB_REFSEL_INTREF
380#endif
382
390#define SDHC_DEV SDHC1
391#define SDHC_DEV_ISR isr_sdhc1
392
394static const sdhc_conf_t sdhc_config[] = {
395 {
396 .sdhc = SDHC1,
397 .cd = GPIO_PIN(PD, 20),
398 .wp = GPIO_UNDEF,
399 },
400};
401
403#define SDHC_CONFIG_NUMOF 1
405
410static const sam0_common_gmac_config_t sam_gmac_config[] = {
411 {
412 .dev = GMAC,
413 .refclk = GPIO_PIN(PA, 14),
414 .txen = GPIO_PIN(PA, 17),
415 .txd0 = GPIO_PIN(PA, 18),
416 .txd1 = GPIO_PIN(PA, 19),
417 .crsdv = GPIO_PIN(PC, 20),
418 .rxd0 = GPIO_PIN(PA, 13),
419 .rxd1 = GPIO_PIN(PA, 12),
420 .rxer = GPIO_PIN(PA, 15),
421 .mdc = GPIO_PIN(PC, 11),
422 .mdio = GPIO_PIN(PC, 12),
423 .rst_pin = GPIO_PIN(PC, 21),
424 .int_pin = GPIO_PIN(PD, 12),
425 }
426};
428
433static const freqm_config_t freqm_config[] = {
434 {
435 .pin = GPIO_PIN(PB, 17),
436 .gclk_src = SAM0_GCLK_32KHZ
437 }
438};
440
441#ifdef __cplusplus
442}
443#endif
444
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:164
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define AT6561_STBY_PIN
ATA6561 STANDBY pin definition.
static const sdhc_conf_t sdhc_config[]
SDHC devices.
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:82
@ UART_PAD_RX_1
select pad 1
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_F
select peripheral function F
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA07
Alias for AIN7.
Definition periph_cpu.h:132
#define SAM0_QSPI_PIN_CLK
Clock.
Definition periph_cpu.h:268
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition periph_cpu.h:130
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI.
Definition periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO.
Definition periph_cpu.h:271
#define SAM0_QSPI_MUX
QSPI mux.
Definition periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PA03
Alias for AIN1.
Definition periph_cpu.h:126
#define SAM0_GCLK_TIMER
4-8 MHz clock for xTimer
Definition periph_cpu.h:78
#define SAM0_GCLK_32KHZ
32 kHz clock
Definition periph_cpu.h:75
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition periph_cpu.h:81
ADC Channel Configuration.
ESP CAN device configuration.
Definition can_esp.h:87
Linux candev configuration.
Frequency meter configuration.
I2C configuration structure.
Definition periph_cpu.h:298
PWM channel configuration data structure.
PWM device configuration.
Ethernet parameters struct.
USB peripheral parameters.
SDHC peripheral configuration.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
UART device configuration.
Definition periph_cpu.h:217