21#include "periph_cpu.h" 
   35        .pm_mask        = PM_APBCMASK_TC3,
 
   36        .gclk_ctrl      = GCLK_CLKCTRL_ID_TCC2_TC3,
 
   37#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL 
   42        .flags          = TC_CTRLA_MODE_COUNT16,
 
   47        .pm_mask        = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
 
   48        .gclk_ctrl      = GCLK_CLKCTRL_ID_TC4_TC5,
 
   49#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL 
   54        .flags          = TC_CTRLA_MODE_COUNT32,
 
   58#define TIMER_0_MAX_VALUE   0xffff 
   61#define TIMER_0_ISR         isr_tc3 
   62#define TIMER_1_ISR         isr_tc4 
   64#define TIMER_NUMOF         ARRAY_SIZE(timer_config) 
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
 
#define SAM0_GCLK_MAIN
120 MHz main clock
 
Timer device configuration.