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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2020 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#include "periph_cpu.h"
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
55#define CLOCK_USE_PLL (1)
56
57#if CLOCK_USE_PLL
58/* edit these values to adjust the PLL output frequency */
59#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
60#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
61/* generate the actual used core clock frequency */
62#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
63#else
64/* edit this value to your needs */
65#define CLOCK_DIV (1U)
66/* generate the actual core clock frequency */
67#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
68#endif
70
75static const tc32_conf_t timer_config[] = {
76 { /* Timer 0 - System Clock */
77 .dev = TC3,
78 .irq = TC3_IRQn,
79 .pm_mask = PM_APBCMASK_TC3,
80 .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
81#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
82 .gclk_src = SAM0_GCLK_1MHZ,
83#else
84 .gclk_src = SAM0_GCLK_MAIN,
85#endif
86 .flags = TC_CTRLA_MODE_COUNT16,
87 },
88 { /* Timer 1 */
89 .dev = TC4,
90 .irq = TC4_IRQn,
91 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
92 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
93#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
94 .gclk_src = SAM0_GCLK_1MHZ,
95#else
96 .gclk_src = SAM0_GCLK_MAIN,
97#endif
98 .flags = TC_CTRLA_MODE_COUNT32,
99 }
100};
101
102#define TIMER_0_MAX_VALUE 0xffff
103
104/* interrupt function name mapping */
105#define TIMER_0_ISR isr_tc3
106#define TIMER_1_ISR isr_tc4
107
108#define TIMER_NUMOF ARRAY_SIZE(timer_config)
110
115static const uart_conf_t uart_config[] = {
116 {
117 .dev = &SERCOM5->USART,
118 .rx_pin = GPIO_PIN(PB,23),
119 .tx_pin = GPIO_PIN(PB,22),
120#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
121 .rts_pin = GPIO_UNDEF,
122 .cts_pin = GPIO_UNDEF,
123#endif
124 .mux = GPIO_MUX_D,
125 .rx_pad = UART_PAD_RX_3,
126 .tx_pad = UART_PAD_TX_2,
127 .flags = UART_FLAG_NONE,
128 .gclk_src = SAM0_GCLK_MAIN,
129 }
130};
131
132/* interrupt function name mapping */
133#define UART_0_ISR isr_sercom5
134
135#define UART_NUMOF ARRAY_SIZE(uart_config)
137
142#define PWM_0_EN 1
143#define PWM_1_EN 1
144
145#if PWM_0_EN
146/* PWM0 channels */
147static const pwm_conf_chan_t pwm_chan0_config[] = {
148 /* GPIO pin, MUX value, TCC channel */
149 { GPIO_PIN(PA, 4), GPIO_MUX_E, 0},
150 { GPIO_PIN(PA, 5), GPIO_MUX_E, 1},
151};
152#endif
153#if PWM_1_EN
154/* PWM1 channels */
155static const pwm_conf_chan_t pwm_chan1_config[] = {
156 /* GPIO pin, MUX value, TCC channel */
157 { GPIO_PIN(PA, 10), GPIO_MUX_E, 0 },
158 { GPIO_PIN(PA, 11), GPIO_MUX_E, 1 },
159};
160#endif
161
162/* PWM device configuration */
163static const pwm_conf_t pwm_config[] = {
164#if PWM_0_EN
165 {TCC_CONFIG(TCC0), pwm_chan0_config, ARRAY_SIZE(pwm_chan0_config), SAM0_GCLK_MAIN},
166#endif
167
168#if PWM_1_EN
169 {TCC_CONFIG(TCC1), pwm_chan1_config, ARRAY_SIZE(pwm_chan1_config), SAM0_GCLK_MAIN},
170#endif
171};
172
173/* number of devices that are actually defined */
174#define PWM_NUMOF ARRAY_SIZE(pwm_config)
176
181
182/* ADC Default values */
183#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
184
185#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
186#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
187#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
188
189static const adc_conf_chan_t adc_channels[] = {
190 /* port, pin, muxpos */
191 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 }, /* A0 */
192 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB02 }, /* A1 */
193 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* A2 */
194 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* A3 */
195 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB08 }, /* A4 */
196 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB09 }, /* A5 */
197 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA09 }, /* A6 */
198 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB03 }, /* A7 */
199};
200
201#define ADC_NUMOF ARRAY_SIZE(adc_channels)
203
208static const i2c_conf_t i2c_config[] = {
209 {
210 .dev = &(SERCOM4->I2CM),
211 .speed = I2C_SPEED_NORMAL,
212 .scl_pin = GPIO_PIN(PB, 9),
213 .sda_pin = GPIO_PIN(PB, 8),
214 .mux = GPIO_MUX_D,
215 .gclk_src = SAM0_GCLK_MAIN,
216 .flags = I2C_FLAG_NONE
217 }
218};
219#define I2C_NUMOF ARRAY_SIZE(i2c_config)
221
226static const spi_conf_t spi_config[] = {
227 { /* Connected to NINA W102 */
228 .dev = &SERCOM2->SPI,
229 .miso_pin = GPIO_PIN(PA, 13),
230 .mosi_pin = GPIO_PIN(PA, 12),
231 .clk_pin = GPIO_PIN(PA, 15),
232 .miso_mux = GPIO_MUX_C,
233 .mosi_mux = GPIO_MUX_C,
234 .clk_mux = GPIO_MUX_C,
235 .miso_pad = SPI_PAD_MISO_1,
236 .mosi_pad = SPI_PAD_MOSI_0_SCK_3,
237 .gclk_src = SAM0_GCLK_MAIN,
238 },
239 {
240 .dev = &SERCOM3->SPI,
241 .miso_pin = GPIO_PIN(PA, 19),
242 .mosi_pin = GPIO_PIN(PA, 16),
243 .clk_pin = GPIO_PIN(PA, 17),
244 .miso_mux = GPIO_MUX_D,
245 .mosi_mux = GPIO_MUX_D,
246 .clk_mux = GPIO_MUX_D,
247 .miso_pad = SPI_PAD_MISO_3,
248 .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
249 .gclk_src = SAM0_GCLK_MAIN,
250 },
251};
252
253#define SPI_NUMOF ARRAY_SIZE(spi_config)
255
260#ifndef RTT_FREQUENCY
261#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
262#endif
264
269static const sam0_common_usb_config_t sam_usbdev_config[] = {
270 {
271 .dm = GPIO_PIN(PA, 24),
272 .dp = GPIO_PIN(PA, 25),
273 .d_mux = GPIO_MUX_G,
274 .device = &USB->DEVICE,
275 .gclk_src = SAM0_GCLK_MAIN,
276 }
277};
279
280#ifdef __cplusplus
281}
282#endif
283
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:82
@ UART_PAD_RX_3
select pad 3
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_1
use pad 1 for MISO line
@ SPI_PAD_MISO_3
use pad 3 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PA
port A
@ UART_PAD_TX_2
select pad 2
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_0_SCK_3
use pad 0 for MOSI, pad 3 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC_INPUTCTRL_MUXPOS_PB08
Alias for PIN2.
Definition periph_cpu.h:120
#define ADC_INPUTCTRL_MUXPOS_PB02
Alias for PIN10.
Definition periph_cpu.h:128
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PB09
Alias for PIN3.
Definition periph_cpu.h:121
#define ADC_INPUTCTRL_MUXPOS_PA09
Alias for PIN17.
Definition periph_cpu.h:135
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:75
#define ADC_INPUTCTRL_MUXPOS_PB03
Alias for PIN11.
Definition periph_cpu.h:129
#define ADC_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:118
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:73
ADC Channel Configuration.
I2C configuration structure.
Definition periph_cpu.h:298
PWM channel configuration data structure.
PWM device configuration.
USB peripheral parameters.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
UART device configuration.
Definition periph_cpu.h:217