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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/*
19 * This board provides an LSE, so enable it before including the default clock config
20 */
21#ifndef CONFIG_BOARD_HAS_LSE
22#define CONFIG_BOARD_HAS_LSE 1
23#endif
24
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
35#ifndef CONFIG_CLOCK_HSE
36#define CONFIG_CLOCK_HSE MHZ(16)
37#endif
38
39#include "periph_cpu.h"
40#include "clk_conf.h"
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
50static const timer_conf_t timer_config[] = {
51 {
52 .dev = TIM3,
53 .max = 0x0000ffff,
54 .rcc_mask = RCC_APB1ENR_TIM3EN,
55 .bus = APB1,
56 .irqn = TIM3_IRQn
57 }
58};
59
60#define TIMER_0_ISR (isr_tim3)
61
62#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
64
69static const uart_conf_t uart_config[] = {
70 {
71 .dev = USART1,
72 .rcc_mask = RCC_APB2ENR_USART1EN,
73 .rx_pin = GPIO_PIN(PORT_A, 10),
74 .tx_pin = GPIO_PIN(PORT_A, 9),
75 .rx_af = GPIO_AF7,
76 .tx_af = GPIO_AF7,
77 .bus = APB2,
78 .irqn = USART1_IRQn
79 },
80};
81
82#define UART_0_ISR (isr_usart1)
83
84#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
86
91static const spi_conf_t spi_config[] = {
92 {
93 .dev = SPI1,
94 .mosi_pin = GPIO_PIN(PORT_A, 7),
95 .miso_pin = GPIO_PIN(PORT_A, 6),
96 .sclk_pin = GPIO_PIN(PORT_A, 5),
97 .cs_pin = SPI_CS_UNDEF,
98 .mosi_af = GPIO_AF5,
99 .miso_af = GPIO_AF5,
100 .sclk_af = GPIO_AF5,
101 .cs_af = GPIO_AF5,
102 .rccmask = RCC_APB2ENR_SPI1EN,
103 .apbbus = APB2
104 },
105 {
106 .dev = SPI2,
107 .mosi_pin = GPIO_PIN(PORT_B, 14),
108 .miso_pin = GPIO_PIN(PORT_B, 15),
109 .sclk_pin = GPIO_PIN(PORT_B, 13),
110 .cs_pin = GPIO_PIN(PORT_B, 12),
111 .mosi_af = GPIO_AF5,
112 .miso_af = GPIO_AF5,
113 .sclk_af = GPIO_AF5,
114 .cs_af = GPIO_AF5,
115 .rccmask = RCC_APB1ENR_SPI2EN,
116 .apbbus = APB1
117 }
118};
119
120#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
122
127static const i2c_conf_t i2c_config[] = {
128 {
129 .dev = I2C1,
130 .speed = I2C_SPEED_NORMAL,
131 .scl_pin = GPIO_PIN(PORT_B, 8),
132 .sda_pin = GPIO_PIN(PORT_B, 9),
133 .scl_af = GPIO_AF4,
134 .sda_af = GPIO_AF4,
135 .bus = APB1,
136 .rcc_mask = RCC_APB1ENR_I2C1EN,
137 .clk = CLOCK_APB1,
138 .irqn = I2C1_EV_IRQn
139 }
140};
141
142#define I2C_0_ISR isr_i2c1_ev
143
144#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
146
151static const adc_conf_t adc_config[] = {
152 { GPIO_PIN(PORT_A, 0), 0 }, /* P14 */
153 { GPIO_PIN(PORT_A, 1), 1 }, /* P15 */
154 { GPIO_PIN(PORT_A, 3), 3 }, /* P17 */
155 /* ADC Temperature channel */
156 { GPIO_UNDEF, 16 },
157 /* ADC VREF channel */
158 { GPIO_UNDEF, 17 },
159};
160
161#define ADC_NUMOF ARRAY_SIZE(adc_config)
163
164#ifdef __cplusplus
165}
166#endif
167
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217