19#ifndef CONFIG_BOARD_HAS_LSE 
   20#define CONFIG_BOARD_HAS_LSE    1 
   24#ifndef CONFIG_BOARD_HAS_HSE 
   25#define CONFIG_BOARD_HAS_HSE    1 
   28#include "periph_cpu.h" 
   48#define ADC_NUMOF           ARRAY_SIZE(adc_config) 
   58        .rcc_mask = RCC_APB2ENR_TIM1EN,
 
   68        .rcc_mask = RCC_APB1ENR_TIM2EN,
 
   78        .rcc_mask = RCC_APB1ENR_TIM3EN,
 
   88        .rcc_mask = RCC_APB1ENR_TIM4EN,
 
   98#define PWM_NUMOF           ARRAY_SIZE(pwm_config) 
  109        .rcc_mask = RCC_APB1ENR_TIM2EN,
 
  116        .rcc_mask = RCC_APB1ENR_TIM3EN,
 
  123        .rcc_mask = RCC_APB1ENR_TIM4EN,
 
  129#define TIMER_0_ISR         isr_tim2 
  130#define TIMER_1_ISR         isr_tim3 
  131#define TIMER_2_ISR         isr_tim4 
  133#define TIMER_NUMOF         ARRAY_SIZE(timer_config) 
  143        .rcc_mask = RCC_APB1ENR_USART2EN,
 
  151        .rcc_mask = RCC_APB2ENR_USART1EN,
 
  159        .rcc_mask = RCC_APB1ENR_USART3EN,
 
  167#define UART_0_ISR          (isr_usart2) 
  168#define UART_1_ISR          (isr_usart1) 
  169#define UART_2_ISR          (isr_usart3) 
  171#define UART_NUMOF          ARRAY_SIZE(uart_config) 
  179#define RTT_FREQUENCY       (16384)       
  196        .rcc_mask = RCC_APB1ENR_I2C1EN,
 
  206        .rcc_mask = RCC_APB1ENR_I2C2EN,
 
  212#define I2C_0_ISR           isr_i2c1_ev 
  213#define I2C_1_ISR           isr_i2c2_ev 
  215#define I2C_NUMOF           ARRAY_SIZE(i2c_config) 
  229        .rccmask = RCC_APB2ENR_SPI1EN,
 
  238        .rccmask = RCC_APB1ENR_SPI2EN,
 
  243#define SPI_NUMOF           ARRAY_SIZE(spi_config) 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
 
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
 
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
 
@ GPIO_AF_OUT_PP
alternate function output - push-pull
 
@ APB1
Advanced Peripheral Bus 1.
 
@ APB2
Advanced Peripheral Bus 2.
 
ADC device configuration.
 
I2C configuration structure.
 
PWM device configuration.
 
SPI device configuration.
 
Timer device configuration.
 
UART device configuration.