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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2020 ML!PA Consulting GmbH
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
20
21#include <stdint.h>
22
23#include "cpu.h"
24#include "periph_cpu.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
62#define CLOCK_USE_PLL (0)
63#define CLOCK_USE_XOSC32_DFLL (1)
64/*
65 * 0: use XOSC32K (always 32.768kHz) to clock GCLK2
66 * 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
67 *
68 * OSCULP32K is factory calibrated to be around 32.768kHz but this values can
69 * be of by a couple off % points, so prefer XOSC32K as default configuration.
70 */
71#define GEN2_ULP32K (0)
72
73#if CLOCK_USE_PLL
74/* edit these values to adjust the PLL output frequency */
75#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
76#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
77/* generate the actual used core clock frequency */
78#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
79#elif CLOCK_USE_XOSC32_DFLL
80/* Settings for 32 kHz external oscillator and 48 MHz DFLL */
81#define CLOCK_CORECLOCK (48000000U)
82#define CLOCK_XOSC32K (32768UL)
83#define CLOCK_8MHZ (1)
84#else
85/* edit this value to your needs */
86#define CLOCK_DIV (1U)
87/* generate the actual core clock frequency */
88#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
89#endif
91
96static const tc32_conf_t timer_config[] = {
97 { /* Timer 0 - System Clock */
98 .dev = TC0,
99 .irq = TC0_IRQn,
100 .pm_mask = PM_APBCMASK_TC0 | PM_APBCMASK_TC1,
101 .gclk_ctrl = GCLK_CLKCTRL_ID_TC0_TC1,
102#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
103 .gclk_src = SAM0_GCLK_1MHZ,
104#else
105 .gclk_src = SAM0_GCLK_MAIN,
106#endif
107 .flags = TC_CTRLA_MODE_COUNT32,
108 },
109 { /* Timer 1 */
110 .dev = TC4,
111 .irq = TC4_IRQn,
112 .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
113 .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
114#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
115 .gclk_src = SAM0_GCLK_1MHZ,
116#else
117 .gclk_src = SAM0_GCLK_MAIN,
118#endif
119 .flags = TC_CTRLA_MODE_COUNT32,
120 }
121};
122
123/* interrupt function name mapping */
124#define TIMER_0_ISR isr_tc0
125#define TIMER_1_ISR isr_tc4
126
127#define TIMER_NUMOF ARRAY_SIZE(timer_config)
129
134static const uart_conf_t uart_config[] = {
135 { /* Virtual COM Port */
136 .dev = &SERCOM3->USART,
137 .rx_pin = GPIO_PIN(PA,25),
138 .tx_pin = GPIO_PIN(PA,24),
139#ifdef MODULE_PERIPH_UART_HW_FC
140 .rts_pin = GPIO_UNDEF,
141 .cts_pin = GPIO_UNDEF,
142#endif
143 .mux = GPIO_MUX_C,
144 .rx_pad = UART_PAD_RX_3,
145 .tx_pad = UART_PAD_TX_2,
146 .flags = UART_FLAG_NONE,
147 .gclk_src = SAM0_GCLK_MAIN,
148 },
149 { /* EXT1 */
150 .dev = &SERCOM4->USART,
151 .rx_pin = GPIO_PIN(PB,9),
152 .tx_pin = GPIO_PIN(PB,8),
153#ifdef MODULE_PERIPH_UART_HW_FC
154 .rts_pin = GPIO_UNDEF,
155 .cts_pin = GPIO_UNDEF,
156#endif
157 .mux = GPIO_MUX_D,
158 .rx_pad = UART_PAD_RX_1,
159 .tx_pad = UART_PAD_TX_0,
160 .flags = UART_FLAG_NONE,
161 .gclk_src = SAM0_GCLK_MAIN,
162 },
163 { /* EXT2 */
164 .dev = &SERCOM0->USART,
165 .rx_pin = GPIO_PIN(PA,9),
166 .tx_pin = GPIO_PIN(PA,8),
167#ifdef MODULE_PERIPH_UART_HW_FC
168 .rts_pin = GPIO_UNDEF,
169 .cts_pin = GPIO_UNDEF,
170#endif
171 .mux = GPIO_MUX_C,
172 .rx_pad = UART_PAD_RX_1,
173 .tx_pad = UART_PAD_TX_0,
174 .flags = UART_FLAG_NONE,
175 .gclk_src = SAM0_GCLK_MAIN,
176 },
177};
178
179/* interrupt function name mapping */
180#define UART_0_ISR isr_sercom3
181#define UART_1_ISR isr_sercom4
182#define UART_2_ISR isr_sercom0
183
184#define UART_NUMOF ARRAY_SIZE(uart_config)
186
191static const spi_conf_t spi_config[] = {
192 { /* EXT1 */
193 .dev = &SERCOM0->SPI,
194 .miso_pin = GPIO_PIN(PA, 4),
195 .mosi_pin = GPIO_PIN(PA, 6),
196 .clk_pin = GPIO_PIN(PA, 7),
197 .miso_mux = GPIO_MUX_D,
198 .mosi_mux = GPIO_MUX_D,
199 .clk_mux = GPIO_MUX_D,
200 .miso_pad = SPI_PAD_MISO_0,
201 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
202 .gclk_src = SAM0_GCLK_MAIN,
203 },
204 { /* EXT2 */
205 .dev = &SERCOM1->SPI,
206 .miso_pin = GPIO_PIN(PA, 16),
207 .mosi_pin = GPIO_PIN(PA, 18),
208 .clk_pin = GPIO_PIN(PA, 19),
209 .miso_mux = GPIO_MUX_C,
210 .mosi_mux = GPIO_MUX_C,
211 .clk_mux = GPIO_MUX_C,
212 .miso_pad = SPI_PAD_MISO_0,
213 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
214 .gclk_src = SAM0_GCLK_MAIN,
215 },
216 { /* EXT3 */
217 .dev = &SERCOM5->SPI,
218 .miso_pin = GPIO_PIN(PB, 16),
219 .mosi_pin = GPIO_PIN(PB, 22),
220 .clk_pin = GPIO_PIN(PB, 23),
221 .miso_mux = GPIO_MUX_C,
222 .mosi_mux = GPIO_MUX_D,
223 .clk_mux = GPIO_MUX_D,
224 .miso_pad = SPI_PAD_MISO_0,
225 .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
226 .gclk_src = SAM0_GCLK_MAIN,
227 },
228};
229
230#define SPI_NUMOF ARRAY_SIZE(spi_config)
232
237static const i2c_conf_t i2c_config[] = {
238 {
239 .dev = &(SERCOM2->I2CM),
240 .speed = I2C_SPEED_NORMAL,
241 .scl_pin = GPIO_PIN(PA, 9),
242 .sda_pin = GPIO_PIN(PA, 8),
243 .mux = GPIO_MUX_D,
244 .gclk_src = SAM0_GCLK_MAIN,
245 .flags = I2C_FLAG_NONE
246 }
247};
248#define I2C_NUMOF ARRAY_SIZE(i2c_config)
250
255#ifndef RTT_FREQUENCY
256#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
257#endif
259
264#define PWM_0_EN 1
265
266#if PWM_0_EN
267/* PWM0 channels */
268static const pwm_conf_chan_t pwm_chan0_config[] = {
269 /* GPIO pin, MUX value, TCC channel */
270 { GPIO_PIN(PA, 14), GPIO_MUX_E, 0 },
271};
272#endif
273
274/* PWM device configuration */
275static const pwm_conf_t pwm_config[] = {
276#if PWM_0_EN
277 { .tim = TC_CONFIG(TC3),
278 .chan = pwm_chan0_config,
279 .chan_numof = ARRAY_SIZE(pwm_chan0_config),
280 .gclk_src = SAM0_GCLK_1MHZ,
281 },
282#endif
283};
284
285/* number of devices that are actually defined */
286#define PWM_NUMOF ARRAY_SIZE(pwm_config)
288
293
294/* ADC Default values */
295#define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV128
296
297#define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
298#define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
299#define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
300
301static const adc_conf_chan_t adc_channels[] = {
302 /* port, pin, muxpos */
303 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB00 }, /* EXT1, pin 3 */
304 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PB01 }, /* EXT1, pin 4 */
305 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA10 }, /* EXT2, pin 3 */
306 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA11 }, /* EXT2, pin 4 */
307 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA02 }, /* EXT3, pin 3 */
308 { .inputctrl = ADC_INPUTCTRL_MUXPOS_PA03 } /* EXT3, pin 4.*/
309};
310
311#define ADC_NUMOF ARRAY_SIZE(adc_channels)
313
318#define DAC_CLOCK SAM0_GCLK_1MHZ
319 /* use Vcc as reference voltage */
320#define DAC_VREF DAC_CTRLB_REFSEL_AVCC
322
323#ifdef __cplusplus
324}
325#endif
326
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition container.h:82
@ UART_PAD_RX_1
select pad 1
@ UART_PAD_RX_3
select pad 3
@ I2C_FLAG_NONE
No flags set.
#define TC_CONFIG(tim)
Static initializer for TC timer configuration.
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ PB
port B
@ PA
port A
@ UART_PAD_TX_0
select pad 0
@ UART_PAD_TX_2
select pad 2
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
#define ADC_INPUTCTRL_MUXPOS_PA10
Alias for PIN18.
Definition periph_cpu.h:136
#define ADC_INPUTCTRL_MUXPOS_PA11
Alias for PIN19.
Definition periph_cpu.h:137
#define ADC_INPUTCTRL_MUXPOS_PB01
Alias for PIN9.
Definition periph_cpu.h:127
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition periph_cpu.h:75
#define ADC_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition periph_cpu.h:118
#define ADC_INPUTCTRL_MUXPOS_PA03
Alias for PIN1.
Definition periph_cpu.h:119
#define ADC_INPUTCTRL_MUXPOS_PB00
Alias for PIN8.
Definition periph_cpu.h:126
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition periph_cpu.h:73
ADC Channel Configuration.
I2C configuration structure.
Definition periph_cpu.h:298
PWM channel configuration data structure.
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
UART device configuration.
Definition periph_cpu.h:217