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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2014 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an HSE */
19#ifndef CONFIG_BOARD_HAS_HSE
20#define CONFIG_BOARD_HAS_HSE 1
21#endif
22
23#include "periph_cpu.h"
24#include "clk_conf.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
34static const timer_conf_t timer_config[] = {
35 {
36 .dev = TIM2,
37 .max = 0xffffffff,
38 .rcc_mask = RCC_APB1ENR_TIM2EN,
39 .bus = APB1,
40 .irqn = TIM2_IRQn
41 }
42};
43
44#define TIMER_0_ISR isr_tim2
45
46#define TIMER_NUMOF ARRAY_SIZE(timer_config)
48
53static const uart_conf_t uart_config[] = {
54 {
55 .dev = USART1,
56 .rcc_mask = RCC_APB2ENR_USART1EN,
57 .rx_pin = GPIO_PIN(PORT_B, 7),
58 .tx_pin = GPIO_PIN(PORT_B, 6),
59 .rx_af = GPIO_AF0,
60 .tx_af = GPIO_AF0,
61 .bus = APB2,
62 .irqn = USART1_IRQn,
63 },
64 {
65 .dev = USART2,
66 .rcc_mask = RCC_APB1ENR_USART2EN,
67 .rx_pin = GPIO_PIN(PORT_A, 3),
68 .tx_pin = GPIO_PIN(PORT_A, 2),
69 .rx_af = GPIO_AF1,
70 .tx_af = GPIO_AF1,
71 .bus = APB1,
72 .irqn = USART2_IRQn
73 }
74};
75
76#define UART_0_ISR (isr_usart1)
77#define UART_1_ISR (isr_usart2)
78
79#define UART_NUMOF ARRAY_SIZE(uart_config)
81
89static const adc_conf_t adc_config[] = {
90 { GPIO_PIN(PORT_C, 0), 10 },
91 { GPIO_PIN(PORT_C, 1), 11 },
92 { GPIO_PIN(PORT_C, 2), 12 },
93 { GPIO_PIN(PORT_C, 3), 13 },
94 { GPIO_PIN(PORT_C, 4), 14 },
95 { GPIO_PIN(PORT_C, 5), 15 },
96 { GPIO_UNDEF, 18 }, /* VBAT */
97};
98
99#define VBAT_ADC ADC_LINE(6)
100#define ADC_NUMOF ARRAY_SIZE(adc_config)
102
107static const spi_conf_t spi_config[] = {
108 {
109 .dev = SPI1,
110 .mosi_pin = GPIO_PIN(PORT_A, 7),
111 .miso_pin = GPIO_PIN(PORT_A, 6),
112 .sclk_pin = GPIO_PIN(PORT_A, 5),
113 .cs_pin = SPI_CS_UNDEF,
114 .mosi_af = GPIO_AF0,
115 .miso_af = GPIO_AF0,
116 .sclk_af = GPIO_AF0,
117 .cs_af = GPIO_AF0,
118 .rccmask = RCC_APB2ENR_SPI1EN,
119 .apbbus = APB2
120 },
121 {
122 .dev = SPI2,
123 .mosi_pin = GPIO_PIN(PORT_B, 15),
124 .miso_pin = GPIO_PIN(PORT_B, 14),
125 .sclk_pin = GPIO_PIN(PORT_B, 13),
126 .cs_pin = SPI_CS_UNDEF,
127 .mosi_af = GPIO_AF0,
128 .miso_af = GPIO_AF0,
129 .sclk_af = GPIO_AF0,
130 .cs_af = GPIO_AF0,
131 .rccmask = RCC_APB1ENR_SPI2EN,
132 .apbbus = APB1
133 }
134};
135
136#define SPI_NUMOF ARRAY_SIZE(spi_config)
138
139#ifdef __cplusplus
140}
141#endif
142
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217