CC26x0/CC13x0 PRCM register definitions. More...
Detailed Description
CC26x0/CC13x0 PRCM register definitions.
Definition in file cc26x0_cc13x0_prcm.h.
#include <cc26xx_cc13xx.h>
Include dependency graph for cc26x0_cc13x0_prcm.h: This graph shows which files directly or indirectly include this file:Go to the source code of this file.
Data Structures | |
| struct | ddi0_osc_regs_t |
| DDI_0_OSC registers. More... | |
| struct | aon_sysctl_regs_t |
| AON_SYSCTL registers. More... | |
| struct | aon_wuc_regs_t |
| AON_WUC registers. More... | |
| struct | aon_rtc_regs_t |
| AON_RTC registers. More... | |
| struct | prcm_regs_t |
| PRCM registers. More... | |
Macros | |
| #define | DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) |
| DDI_0_OSC register bank. | |
| #define | AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE)) |
| AON_SYSCTL register bank. | |
| #define | AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) |
| AON_WUC register bank. | |
| #define | AON_RTC_CTL_RTC_UPD_EN 0x00000002 |
| RTC_UPD is a 16 KHz signal used to sync up the radio timer. | |
| #define | AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) |
| AON_RTC register bank. | |
| #define | PRCM ((prcm_regs_t *) (PRCM_BASE)) |
| PRCM register bank. | |
| #define | PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) |
| PRCM register bank (nonbuf) | |
| #define | DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask 0x6 |
| DDI_0_OSC register values. | |
| #define | DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC 0x0 |
| #define | DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC 0x4 |
| #define | DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC 0x8 |
| #define | DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC 0xC |
| #define | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask 0x60 |
| #define | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF 0x00 /* 31.25kHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF 0x20 /* 31.25kHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF 0x40 /* 32kHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF 0x60 /* 32.768kHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask 0x180 |
| #define | DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF 0x000 /* 48MHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF 0x080 /* 48MHz */ |
| #define | DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF 0x100 /* 24MHz */ |
| #define | DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask 0x6000000 |
| #define | DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 |
| #define | DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 |
| #define | DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 |
| #define | DDI0_OSC_BASE 0x400CA000 |
| DDI0_OSC base address. | |
| #define | AON_SYSCTL_BASE 0x40090000 |
| AON_SYSCTL base address. | |
| #define | MCUCLK_PWR_DWN_SRC 0x1 /* SCLK_LF in powerdown (no clock elsewise) */ |
| AON_WUC register values. | |
| #define | MCUCLK_PWR_DWN_SRC_mask 0x3 |
| #define | MCUCLK_RCOSC_HF_CAL_DONE 0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */ |
| #define | AUXCLK_SRC_HF 0x1 /* SCLK for AUX */ |
| #define | AUXCLK_SRC_LF 0x4 |
| #define | AUXCLK_SRC_mask 0x7 /* guaranteed to be glitchless */ |
| #define | AUXCLK_SCLK_HF_DIV_pos 8 /* don't set while SCLK_HF active for AUX */ |
| #define | AUXCLK_SCLK_HF_DIV_mask 0x700 /* divisor will be 2^(value+1) */ |
| #define | AUXCLK_PWR_DWN_SRC_pos 11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */ |
| #define | AUXCLK_PWR_DWN_SRC_mask 0x1800 /* datasheet is confusing.. */ |
| #define | MCUCFG_SRAM_RET_OFF 0x0 /* no retention for any SRAM-bank */ |
| #define | MCUCFG_SRAM_RET_B0 0x1 |
| #define | MCUCFG_SRAM_RET_B01 0x3 |
| #define | MCUCFG_SRAM_RET_B012 0x7 |
| #define | MCUCFG_SRAM_RET_B0124 0xF /* retention for banks 0, 1, 2, and 3 */ |
| #define | MCUCFG_SRAM_FIXED_WU_EN 0x100 |
| #define | MCUCFG_SRAM_VIRT_OFF 0x200 |
| #define | AUXCFG_RAM_RET_EN 0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */ |
| #define | AUXCTL_AUX_FORCE_ON 0x1 |
| #define | AUXCTL_SWEV 0x2 |
| #define | AUXCTL_SCE_RUN_EN 0x3 |
| #define | AUXCTL_RESET_REQ 0x80000000 |
| #define | PWRSTAT_AUX_RESET_DONE 0x2 |
| #define | PWRSTAT_AUX_BUS_CONNECTED 0x4 |
| #define | PWRSTAT_MCU_PD_ON 0x10 |
| #define | PWRSTAT_AUX_PD_ON 0x20 |
| #define | PWRSTAT_JTAG_PD_ON 0x40 |
| #define | PWRSTAT_AUX_PWR_DNW 0x200 |
| #define | SHUTDOWN_EN 0x1 /* register/cancel shutdown request */ |
| #define | AONWUC_CTL0_MCU_SRAM_ERASE 0x4 |
| #define | AONWUC_CTL0_AUX_SRAM_ERASE 0x8 |
| #define | AONWUC_CTL0_PWR_DWN_DIS 0x10 /* disable powerdown on request */ |
| #define | AONWUC_CTL1_MCU_WARM_RESET 0x1 /* last MCU reset was a warm reset */ |
| #define | AONWUC_CTL1_MCU_RESET_SRC 0x2 /* JTAG was source of last reset (MCU SW elsewise) */ |
| #define | RECHARGECFG_PER_E_mask 0x00000007 /* number of 32KHz clocks between activation of recharge controller: */ |
| #define | RECHARGECFG_PER_M_mask 0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */ |
| #define | RECHARGECFG_MAX_PER_E_mask 0x00000700 /* maximum period the recharge algorithm can take */ |
| #define | RECHARGECFG_MAX_PER_M_mask 0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */ |
| #define | RECHARGECFG_C1_mask 0x000F0000 /* i resign */ |
| #define | RECHARGECFG_C2_mask 0x000F0000 |
| #define | RECHARGECFG_ADAPTIVE_EN 0x80000000 |
| #define | RECHARGESTAT_MAX_USED_PER_mask 0x0FFFF |
| #define | RECHARGESTAT_VDDR_SMPLS_mask 0xF0000 |
| #define | OSCCFG_PER_E_mask 0x07 /* number of 32KHz clocks between oscillator amplitude calibrations */ |
| #define | OSCCFG_PER_M_mask 0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */ |
| #define | JTAGCFG_JTAG_PD_FORCE_ON 0x10 |
| #define | AON_WUC_BASE 0x40091000 |
| AON_WUC base address. | |
| #define | AON_RTC_BASE (PERIPH_BASE + 0x92000) |
| AON_RTC base address. | |
| #define | CLKLOADCTL_LOAD 0x1 |
| PRCM register values. | |
| #define | CLKLOADCTL_LOADDONE 0x2 |
| #define | PDCTL0_RFC_ON 0x1 |
| #define | PDCTL0_SERIAL_ON 0x2 |
| #define | PDCTL0_PERIPH_ON 0x4 |
| #define | PDSTAT0_RFC_ON 0x1 |
| #define | PDSTAT0_SERIAL_ON 0x2 |
| #define | PDSTAT0_PERIPH_ON 0x4 |
| #define | PDCTL1_CPU_ON 0x2 |
| #define | PDCTL1_RFC_ON 0x4 |
| #define | PDCTL1_VIMS_ON 0x8 |
| #define | PDSTAT1_CPU_ON 0x2 |
| #define | PDSTAT1_RFC_ON 0x4 |
| #define | PDSTAT1_VIMS_ON 0x8 |
| #define | GPIOCLKGR_CLK_EN 0x1 |
| #define | I2CCLKGR_CLK_EN 0x1 |
| #define | UARTCLKGR_CLK_EN_UART0 0x1 |
| #define | GPIOCLKGS_CLK_EN 0x1 |
| #define | I2CCLKGS_CLK_EN 0x1 |
| #define | UARTCLKGS_CLK_EN_UART0 0x1 |
| #define | GPIOCLKGDS_CLK_EN 0x1 |
| #define | I2CCLKGDS_CLK_EN 0x1 |
| #define | UARTCLKGDS_CLK_EN_UART0 0x1 |
| #define | PRCM_BASE (PERIPH_BASE + 0x82000) |
| PRCM base address. | |
| #define | PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) |
| PRCM base address (nonbuf) | |
Macro Definition Documentation
◆ AON_RTC
| #define AON_RTC ((aon_rtc_regs_t *) (AON_RTC_BASE)) |
AON_RTC register bank.
Definition at line 227 of file cc26x0_cc13x0_prcm.h.
◆ AON_RTC_CTL_RTC_UPD_EN
| #define AON_RTC_CTL_RTC_UPD_EN 0x00000002 |
RTC_UPD is a 16 KHz signal used to sync up the radio timer.
The 16 Khz is SCLK_LF divided by 2
0h = RTC_UPD signal is forced to 0 1h = RTC_UPD signal is toggling @16 kHz
Definition at line 218 of file cc26x0_cc13x0_prcm.h.
◆ AON_SYSCTL
| #define AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE)) |
AON_SYSCTL register bank.
Definition at line 96 of file cc26x0_cc13x0_prcm.h.
◆ AON_WUC
| #define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE)) |
AON_WUC register bank.
Definition at line 192 of file cc26x0_cc13x0_prcm.h.
◆ AONWUC_CTL0_AUX_SRAM_ERASE
| #define AONWUC_CTL0_AUX_SRAM_ERASE 0x8 |
Definition at line 162 of file cc26x0_cc13x0_prcm.h.
◆ AONWUC_CTL0_MCU_SRAM_ERASE
| #define AONWUC_CTL0_MCU_SRAM_ERASE 0x4 |
Definition at line 161 of file cc26x0_cc13x0_prcm.h.
◆ AONWUC_CTL0_PWR_DWN_DIS
| #define AONWUC_CTL0_PWR_DWN_DIS 0x10 /* disable powerdown on request */ |
Definition at line 163 of file cc26x0_cc13x0_prcm.h.
◆ AONWUC_CTL1_MCU_RESET_SRC
| #define AONWUC_CTL1_MCU_RESET_SRC 0x2 /* JTAG was source of last reset (MCU SW elsewise) */ |
Definition at line 166 of file cc26x0_cc13x0_prcm.h.
◆ AONWUC_CTL1_MCU_WARM_RESET
| #define AONWUC_CTL1_MCU_WARM_RESET 0x1 /* last MCU reset was a warm reset */ |
Definition at line 165 of file cc26x0_cc13x0_prcm.h.
◆ AUXCFG_RAM_RET_EN
| #define AUXCFG_RAM_RET_EN 0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */ |
Definition at line 145 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_PWR_DWN_SRC_mask
| #define AUXCLK_PWR_DWN_SRC_mask 0x1800 /* datasheet is confusing.. */ |
Definition at line 135 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_PWR_DWN_SRC_pos
| #define AUXCLK_PWR_DWN_SRC_pos 11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */ |
Definition at line 134 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_SCLK_HF_DIV_mask
| #define AUXCLK_SCLK_HF_DIV_mask 0x700 /* divisor will be 2^(value+1) */ |
Definition at line 133 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_SCLK_HF_DIV_pos
| #define AUXCLK_SCLK_HF_DIV_pos 8 /* don't set while SCLK_HF active for AUX */ |
Definition at line 132 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_SRC_HF
| #define AUXCLK_SRC_HF 0x1 /* SCLK for AUX */ |
Definition at line 129 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_SRC_LF
| #define AUXCLK_SRC_LF 0x4 |
Definition at line 130 of file cc26x0_cc13x0_prcm.h.
◆ AUXCLK_SRC_mask
| #define AUXCLK_SRC_mask 0x7 /* guaranteed to be glitchless */ |
Definition at line 131 of file cc26x0_cc13x0_prcm.h.
◆ AUXCTL_AUX_FORCE_ON
| #define AUXCTL_AUX_FORCE_ON 0x1 |
Definition at line 147 of file cc26x0_cc13x0_prcm.h.
◆ AUXCTL_RESET_REQ
| #define AUXCTL_RESET_REQ 0x80000000 |
Definition at line 150 of file cc26x0_cc13x0_prcm.h.
◆ AUXCTL_SCE_RUN_EN
| #define AUXCTL_SCE_RUN_EN 0x3 |
Definition at line 149 of file cc26x0_cc13x0_prcm.h.
◆ AUXCTL_SWEV
| #define AUXCTL_SWEV 0x2 |
Definition at line 148 of file cc26x0_cc13x0_prcm.h.
◆ CLKLOADCTL_LOAD
| #define CLKLOADCTL_LOAD 0x1 |
PRCM register values.
Definition at line 311 of file cc26x0_cc13x0_prcm.h.
◆ CLKLOADCTL_LOADDONE
| #define CLKLOADCTL_LOADDONE 0x2 |
Definition at line 312 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC
| #define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE)) |
DDI_0_OSC register bank.
Definition at line 78 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF
| #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF 0x00 /* 31.25kHz */ |
Definition at line 54 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF
| #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF 0x40 /* 32kHz */ |
Definition at line 56 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask
| #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask 0x60 |
Definition at line 53 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF
| #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF 0x20 /* 31.25kHz */ |
Definition at line 55 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF
| #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF 0x60 /* 32.768kHz */ |
Definition at line 57 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF
| #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF 0x000 /* 48MHz */ |
Definition at line 59 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF
| #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF 0x080 /* 48MHz */ |
Definition at line 60 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask
| #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask 0x180 |
Definition at line 58 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF
| #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF 0x100 /* 24MHz */ |
Definition at line 61 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL
| #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 |
Definition at line 63 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL
| #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 |
Definition at line 64 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask
| #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask 0x6000000 |
Definition at line 62 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC
| #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC 0x0 |
Definition at line 49 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC
| #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC 0x4 |
Definition at line 50 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC
| #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC 0x8 |
Definition at line 51 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC
| #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC 0xC |
Definition at line 52 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask
| #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask 0x6 |
DDI_0_OSC register values.
Definition at line 48 of file cc26x0_cc13x0_prcm.h.
◆ DDI_0_OSC_CTL0_XTAL_IS_24M
| #define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 |
Definition at line 65 of file cc26x0_cc13x0_prcm.h.
◆ GPIOCLKGDS_CLK_EN
| #define GPIOCLKGDS_CLK_EN 0x1 |
Definition at line 338 of file cc26x0_cc13x0_prcm.h.
◆ GPIOCLKGR_CLK_EN
| #define GPIOCLKGR_CLK_EN 0x1 |
Definition at line 330 of file cc26x0_cc13x0_prcm.h.
◆ GPIOCLKGS_CLK_EN
| #define GPIOCLKGS_CLK_EN 0x1 |
Definition at line 334 of file cc26x0_cc13x0_prcm.h.
◆ I2CCLKGDS_CLK_EN
| #define I2CCLKGDS_CLK_EN 0x1 |
Definition at line 339 of file cc26x0_cc13x0_prcm.h.
◆ I2CCLKGR_CLK_EN
| #define I2CCLKGR_CLK_EN 0x1 |
Definition at line 331 of file cc26x0_cc13x0_prcm.h.
◆ I2CCLKGS_CLK_EN
| #define I2CCLKGS_CLK_EN 0x1 |
Definition at line 335 of file cc26x0_cc13x0_prcm.h.
◆ JTAGCFG_JTAG_PD_FORCE_ON
| #define JTAGCFG_JTAG_PD_FORCE_ON 0x10 |
Definition at line 182 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_FIXED_WU_EN
| #define MCUCFG_SRAM_FIXED_WU_EN 0x100 |
Definition at line 142 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_RET_B0
| #define MCUCFG_SRAM_RET_B0 0x1 |
Definition at line 138 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_RET_B01
| #define MCUCFG_SRAM_RET_B01 0x3 |
Definition at line 139 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_RET_B012
| #define MCUCFG_SRAM_RET_B012 0x7 |
Definition at line 140 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_RET_B0124
| #define MCUCFG_SRAM_RET_B0124 0xF /* retention for banks 0, 1, 2, and 3 */ |
Definition at line 141 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_RET_OFF
| #define MCUCFG_SRAM_RET_OFF 0x0 /* no retention for any SRAM-bank */ |
Definition at line 137 of file cc26x0_cc13x0_prcm.h.
◆ MCUCFG_SRAM_VIRT_OFF
| #define MCUCFG_SRAM_VIRT_OFF 0x200 |
Definition at line 143 of file cc26x0_cc13x0_prcm.h.
◆ MCUCLK_PWR_DWN_SRC
| #define MCUCLK_PWR_DWN_SRC 0x1 /* SCLK_LF in powerdown (no clock elsewise) */ |
AON_WUC register values.
Definition at line 125 of file cc26x0_cc13x0_prcm.h.
◆ MCUCLK_PWR_DWN_SRC_mask
| #define MCUCLK_PWR_DWN_SRC_mask 0x3 |
Definition at line 126 of file cc26x0_cc13x0_prcm.h.
◆ MCUCLK_RCOSC_HF_CAL_DONE
| #define MCUCLK_RCOSC_HF_CAL_DONE 0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */ |
Definition at line 127 of file cc26x0_cc13x0_prcm.h.
◆ OSCCFG_PER_E_mask
| #define OSCCFG_PER_E_mask 0x07 /* number of 32KHz clocks between oscillator amplitude calibrations */ |
Definition at line 179 of file cc26x0_cc13x0_prcm.h.
◆ OSCCFG_PER_M_mask
| #define OSCCFG_PER_M_mask 0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */ |
Definition at line 180 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL0_PERIPH_ON
| #define PDCTL0_PERIPH_ON 0x4 |
Definition at line 316 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL0_RFC_ON
| #define PDCTL0_RFC_ON 0x1 |
Definition at line 314 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL0_SERIAL_ON
| #define PDCTL0_SERIAL_ON 0x2 |
Definition at line 315 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL1_CPU_ON
| #define PDCTL1_CPU_ON 0x2 |
Definition at line 322 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL1_RFC_ON
| #define PDCTL1_RFC_ON 0x4 |
Definition at line 323 of file cc26x0_cc13x0_prcm.h.
◆ PDCTL1_VIMS_ON
| #define PDCTL1_VIMS_ON 0x8 |
Definition at line 324 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT0_PERIPH_ON
| #define PDSTAT0_PERIPH_ON 0x4 |
Definition at line 320 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT0_RFC_ON
| #define PDSTAT0_RFC_ON 0x1 |
Definition at line 318 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT0_SERIAL_ON
| #define PDSTAT0_SERIAL_ON 0x2 |
Definition at line 319 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT1_CPU_ON
| #define PDSTAT1_CPU_ON 0x2 |
Definition at line 326 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT1_RFC_ON
| #define PDSTAT1_RFC_ON 0x4 |
Definition at line 327 of file cc26x0_cc13x0_prcm.h.
◆ PDSTAT1_VIMS_ON
| #define PDSTAT1_VIMS_ON 0x8 |
Definition at line 328 of file cc26x0_cc13x0_prcm.h.
◆ PRCM
| #define PRCM ((prcm_regs_t *) (PRCM_BASE)) |
PRCM register bank.
Definition at line 351 of file cc26x0_cc13x0_prcm.h.
◆ PRCM_BASE_NONBUF
| #define PRCM_BASE_NONBUF (PERIPH_BASE_NONBUF + 0x82000) |
PRCM base address (nonbuf)
Definition at line 348 of file cc26x0_cc13x0_prcm.h.
◆ PRCM_NONBUF
| #define PRCM_NONBUF ((prcm_regs_t *) (PRCM_BASE_NONBUF)) |
PRCM register bank (nonbuf)
Definition at line 352 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_AUX_BUS_CONNECTED
| #define PWRSTAT_AUX_BUS_CONNECTED 0x4 |
Definition at line 153 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_AUX_PD_ON
| #define PWRSTAT_AUX_PD_ON 0x20 |
Definition at line 155 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_AUX_PWR_DNW
| #define PWRSTAT_AUX_PWR_DNW 0x200 |
Definition at line 157 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_AUX_RESET_DONE
| #define PWRSTAT_AUX_RESET_DONE 0x2 |
Definition at line 152 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_JTAG_PD_ON
| #define PWRSTAT_JTAG_PD_ON 0x40 |
Definition at line 156 of file cc26x0_cc13x0_prcm.h.
◆ PWRSTAT_MCU_PD_ON
| #define PWRSTAT_MCU_PD_ON 0x10 |
Definition at line 154 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_ADAPTIVE_EN
| #define RECHARGECFG_ADAPTIVE_EN 0x80000000 |
Definition at line 174 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_C1_mask
| #define RECHARGECFG_C1_mask 0x000F0000 /* i resign */ |
Definition at line 172 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_C2_mask
| #define RECHARGECFG_C2_mask 0x000F0000 |
Definition at line 173 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_MAX_PER_E_mask
| #define RECHARGECFG_MAX_PER_E_mask 0x00000700 /* maximum period the recharge algorithm can take */ |
Definition at line 170 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_MAX_PER_M_mask
| #define RECHARGECFG_MAX_PER_M_mask 0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */ |
Definition at line 171 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_PER_E_mask
| #define RECHARGECFG_PER_E_mask 0x00000007 /* number of 32KHz clocks between activation of recharge controller: */ |
Definition at line 168 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGECFG_PER_M_mask
| #define RECHARGECFG_PER_M_mask 0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */ |
Definition at line 169 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGESTAT_MAX_USED_PER_mask
| #define RECHARGESTAT_MAX_USED_PER_mask 0x0FFFF |
Definition at line 176 of file cc26x0_cc13x0_prcm.h.
◆ RECHARGESTAT_VDDR_SMPLS_mask
| #define RECHARGESTAT_VDDR_SMPLS_mask 0xF0000 |
Definition at line 177 of file cc26x0_cc13x0_prcm.h.
◆ SHUTDOWN_EN
| #define SHUTDOWN_EN 0x1 /* register/cancel shutdown request */ |
Definition at line 159 of file cc26x0_cc13x0_prcm.h.
◆ UARTCLKGDS_CLK_EN_UART0
| #define UARTCLKGDS_CLK_EN_UART0 0x1 |
Definition at line 340 of file cc26x0_cc13x0_prcm.h.
◆ UARTCLKGR_CLK_EN_UART0
| #define UARTCLKGR_CLK_EN_UART0 0x1 |
Definition at line 332 of file cc26x0_cc13x0_prcm.h.
◆ UARTCLKGS_CLK_EN_UART0
| #define UARTCLKGS_CLK_EN_UART0 0x1 |
Definition at line 336 of file cc26x0_cc13x0_prcm.h.
