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Data Structures | Macros
cc26x2_cc13x2_prcm.h File Reference
CPU » TI CC26x2, CC13x2 » TI CC26x2, CC13x2 definitions

CC26x2, CC13x2 PRCM register definitions. More...

Detailed Description

CC26x2, CC13x2 PRCM register definitions.

Definition in file cc26x2_cc13x2_prcm.h.

#include <cc26xx_cc13xx.h>
+ Include dependency graph for cc26x2_cc13x2_prcm.h:
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Go to the source code of this file.

Data Structures

struct  ddi0_osc_regs_t
 DDI_0_OSC registers. More...
 
struct  ddi0_osc_regs_m16_t
 DDI_0_OSC registers with masked 16-bit access. More...
 
struct  aon_pmctl_regs_t
 AON_PMCTL registers. More...
 
struct  aon_rtc_regs_t
 AON_RTC registers. More...
 
struct  prcm_regs_t
 PRCM registers. More...
 

Macros

#define DDI_0_OSC   ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
 DDI_0_OSC register bank.
 
#define DDI_0_OSC_M16   ((ddi0_osc_regs_m16_t *) (DDI0_OSC_BASE_M16))
 DDI_0_OSC 16-bit masked access register bank.
 
#define AON_PMCTL   ((aon_pmctl_regs_t *) (AON_PMCTL_BASE))
 AON_PMCTL register bank.
 
#define AON_RTC_CTL_RTC_UPD_EN   0x00000002
 RTC_UPD is a 16 KHz signal used to sync up the radio timer.
 
#define AON_RTC   ((aon_rtc_regs_t *) (AON_RTC_BASE))
 AON_RTC register bank.
 
#define PRCM   ((prcm_regs_t *) (PRCM_BASE))
 PRCM register bank.
 
#define PRCM_NONBUF   ((prcm_regs_t *) (PRCM_BASE_NONBUF))
 PRCM register bank (nonbuf)
 
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_m   0x00000001
 DDI_0_OSC register values.
 
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_s   0
 
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC   0x00000001
 
#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC   0x00000000
 
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_m   0x0000000C
 
#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_s   2
 
#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL   0x00000180
 
#define DDI_0_OSC_CTL0_CLK_LOSS_EN   0x00000200
 
#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS   0x00000400
 
#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE   0x00000800
 
#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED   0x00001000
 
#define DDI_0_OSC_CTL0_HPOSC_MODE_EN   0x00004000
 
#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_m   0x01000000
 
#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION   0x02000000
 
#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION   0x0C000000
 
#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL   0x10000000
 
#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL   0x20000000
 
#define DDI_0_OSC_CTL0_XTAL_IS_24M   0x80000000
 
#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING   0x00000001
 
#define DDI_0_OSC_STAT0_SCLK_HF_SRC_m   0x10000000
 
#define DDI_0_OSC_STAT0_SCLK_HF_SRC_s   28
 
#define DDI_0_OSC_STAT0_SCLK_LF_SRC_m   0x60000000
 
#define DDI_0_OSC_STAT0_SCLK_LF_SRC_s   29
 
#define DDI_DIR   0x00000000
 
#define DDI_SET   0x00000080
 
#define DDI_CLR   0x00000100
 
#define DDI_MASK4B   0x00000200
 
#define DDI_MASK8B   0x00000300
 
#define DDI_MASK16B   0x00000400
 
#define DDI0_OSC_BASE   (PERIPH_BASE + 0xCA000)
 DDI0_OSC base address.
 
#define DDI0_OSC_BASE_M16   (DDI0_OSC_BASE + DDI_MASK16B)
 DDI0_OSC 16-bit masked access base address.
 
#define OSC_RCOSC_HF   0x00000000
 SCLK_HF oscillators.
 
#define OSC_XOSC_HF   0x00000001
 External HF crystal oscillator.
 
#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS   0x00000001
 AON_PMTCTL register values.
 
#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_m   0x02000000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_m   0x01000000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_m   0x00020000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_m   0x00010000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_1_m   0x00002000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_0_m   0x00001000
 
#define AON_PMCTL_RESETCTL_BOOT_DET_0_s   12
 
#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_m   0x00000010
 
#define AON_PMCTL_BASE   (PERIPH_BASE + 0x90000)
 AON_PMCTL base address.
 
#define AON_RTC_BASE   (PERIPH_BASE + 0x92000)
 AON_RTC base address.
 
#define CLKLOADCTL_LOAD   0x1
 PRCM register values.
 
#define CLKLOADCTL_LOADDONE   0x2
 
#define PDCTL0_RFC_ON   0x1
 
#define PDCTL0_SERIAL_ON   0x2
 
#define PDCTL0_PERIPH_ON   0x4
 
#define PDSTAT0_RFC_ON   0x1
 
#define PDSTAT0_SERIAL_ON   0x2
 
#define PDSTAT0_PERIPH_ON   0x4
 
#define PDCTL1_CPU_ON   0x2
 
#define PDCTL1_RFC_ON   0x4
 
#define PDCTL1_VIMS_ON   0x8
 
#define PDSTAT1_CPU_ON   0x2
 
#define PDSTAT1_RFC_ON   0x4
 
#define PDSTAT1_VIMS_ON   0x8
 
#define GPIOCLKGR_CLK_EN   0x1
 
#define I2CCLKGR_CLK_EN   0x1
 
#define UARTCLKGR_CLK_EN_UART0   0x1
 
#define UARTCLKGR_CLK_EN_UART1   0x2
 
#define GPIOCLKGS_CLK_EN   0x1
 
#define I2CCLKGS_CLK_EN   0x1
 
#define UARTCLKGS_CLK_EN_UART0   0x1
 
#define UARTCLKGS_CLK_EN_UART1   0x2
 
#define GPIOCLKGDS_CLK_EN   0x1
 
#define I2CCLKGDS_CLK_EN   0x1
 
#define UARTCLKGDS_CLK_EN_UART0   0x1
 
#define UARTCLKGDS_CLK_EN_UART1   0x2
 
#define PRCM_BASE   (PERIPH_BASE + 0x82000)
 PRCM base address.
 
#define PRCM_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x82000)
 PRCM base address (nonbuf)
 
void osc_hf_source_switch (uint32_t osc)
 DDI_0_OSC functions.
 

Macro Definition Documentation

◆ AON_PMCTL

#define AON_PMCTL   ((aon_pmctl_regs_t *) (AON_PMCTL_BASE))

AON_PMCTL register bank.

Definition at line 204 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_m

#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_m   0x01000000

Definition at line 182 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_0_m

#define AON_PMCTL_RESETCTL_BOOT_DET_0_m   0x00001000

Definition at line 186 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_0_s

#define AON_PMCTL_RESETCTL_BOOT_DET_0_s   12

Definition at line 187 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_0_SET_m

#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_m   0x00010000

Definition at line 184 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_m

#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_m   0x02000000

Definition at line 181 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_1_m

#define AON_PMCTL_RESETCTL_BOOT_DET_1_m   0x00002000

Definition at line 185 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_BOOT_DET_1_SET_m

#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_m   0x00020000

Definition at line 183 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_RESETCTL_MCU_WARM_RESET_m

#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_m   0x00000010

Definition at line 188 of file cc26x2_cc13x2_prcm.h.

◆ AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS

#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS   0x00000001

AON_PMTCTL register values.

Definition at line 180 of file cc26x2_cc13x2_prcm.h.

◆ AON_RTC

#define AON_RTC   ((aon_rtc_regs_t *) (AON_RTC_BASE))

AON_RTC register bank.

Definition at line 240 of file cc26x2_cc13x2_prcm.h.

◆ AON_RTC_CTL_RTC_UPD_EN

#define AON_RTC_CTL_RTC_UPD_EN   0x00000002

RTC_UPD is a 16 KHz signal used to sync up the radio timer.

The 16 Khz is SCLK_LF divided by 2

0h = RTC_UPD signal is forced to 0 1h = RTC_UPD signal is toggling @16 kHz

Definition at line 232 of file cc26x2_cc13x2_prcm.h.

◆ CLKLOADCTL_LOAD

#define CLKLOADCTL_LOAD   0x1

PRCM register values.

Definition at line 338 of file cc26x2_cc13x2_prcm.h.

◆ CLKLOADCTL_LOADDONE

#define CLKLOADCTL_LOADDONE   0x2

Definition at line 339 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC

#define DDI_0_OSC   ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))

DDI_0_OSC register bank.

Definition at line 126 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL

#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL   0x00000180

Definition at line 84 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL

#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL   0x10000000

Definition at line 93 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL

#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL   0x20000000

Definition at line 94 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_m

#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_m   0x01000000

Definition at line 90 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_CLK_LOSS_EN

#define DDI_0_OSC_CTL0_CLK_LOSS_EN   0x00000200

Definition at line 85 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION

#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION   0x02000000

Definition at line 91 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_DOUBLER_START_DURATION

#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION   0x0C000000

Definition at line 92 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_HPOSC_MODE_EN

#define DDI_0_OSC_CTL0_HPOSC_MODE_EN   0x00004000

Definition at line 89 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED

#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED   0x00001000

Definition at line 88 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_m

#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_m   0x00000001

DDI_0_OSC register values.

Definition at line 78 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC

#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC   0x00000000

Definition at line 81 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_s

#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_s   0

Definition at line 79 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC

#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC   0x00000001

Definition at line 80 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_m

#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_m   0x0000000C

Definition at line 82 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_s

#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_s   2

Definition at line 83 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE

#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE   0x00000800

Definition at line 87 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS

#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS   0x00000400

Definition at line 86 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_CTL0_XTAL_IS_24M

#define DDI_0_OSC_CTL0_XTAL_IS_24M   0x80000000

Definition at line 95 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_M16

#define DDI_0_OSC_M16   ((ddi0_osc_regs_m16_t *) (DDI0_OSC_BASE_M16))

DDI_0_OSC 16-bit masked access register bank.

Definition at line 130 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING

#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING   0x00000001

Definition at line 96 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_STAT0_SCLK_HF_SRC_m

#define DDI_0_OSC_STAT0_SCLK_HF_SRC_m   0x10000000

Definition at line 97 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_STAT0_SCLK_HF_SRC_s

#define DDI_0_OSC_STAT0_SCLK_HF_SRC_s   28

Definition at line 98 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_STAT0_SCLK_LF_SRC_m

#define DDI_0_OSC_STAT0_SCLK_LF_SRC_m   0x60000000

Definition at line 99 of file cc26x2_cc13x2_prcm.h.

◆ DDI_0_OSC_STAT0_SCLK_LF_SRC_s

#define DDI_0_OSC_STAT0_SCLK_LF_SRC_s   29

Definition at line 100 of file cc26x2_cc13x2_prcm.h.

◆ GPIOCLKGDS_CLK_EN

#define GPIOCLKGDS_CLK_EN   0x1

Definition at line 367 of file cc26x2_cc13x2_prcm.h.

◆ GPIOCLKGR_CLK_EN

#define GPIOCLKGR_CLK_EN   0x1

Definition at line 357 of file cc26x2_cc13x2_prcm.h.

◆ GPIOCLKGS_CLK_EN

#define GPIOCLKGS_CLK_EN   0x1

Definition at line 362 of file cc26x2_cc13x2_prcm.h.

◆ I2CCLKGDS_CLK_EN

#define I2CCLKGDS_CLK_EN   0x1

Definition at line 368 of file cc26x2_cc13x2_prcm.h.

◆ I2CCLKGR_CLK_EN

#define I2CCLKGR_CLK_EN   0x1

Definition at line 358 of file cc26x2_cc13x2_prcm.h.

◆ I2CCLKGS_CLK_EN

#define I2CCLKGS_CLK_EN   0x1

Definition at line 363 of file cc26x2_cc13x2_prcm.h.

◆ OSC_RCOSC_HF

#define OSC_RCOSC_HF   0x00000000

SCLK_HF oscillators.

Internal HF RC oscillator

Definition at line 136 of file cc26x2_cc13x2_prcm.h.

◆ OSC_XOSC_HF

#define OSC_XOSC_HF   0x00000001

External HF crystal oscillator.

Definition at line 137 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL0_PERIPH_ON

#define PDCTL0_PERIPH_ON   0x4

Definition at line 343 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL0_RFC_ON

#define PDCTL0_RFC_ON   0x1

Definition at line 341 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL0_SERIAL_ON

#define PDCTL0_SERIAL_ON   0x2

Definition at line 342 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL1_CPU_ON

#define PDCTL1_CPU_ON   0x2

Definition at line 349 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL1_RFC_ON

#define PDCTL1_RFC_ON   0x4

Definition at line 350 of file cc26x2_cc13x2_prcm.h.

◆ PDCTL1_VIMS_ON

#define PDCTL1_VIMS_ON   0x8

Definition at line 351 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT0_PERIPH_ON

#define PDSTAT0_PERIPH_ON   0x4

Definition at line 347 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT0_RFC_ON

#define PDSTAT0_RFC_ON   0x1

Definition at line 345 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT0_SERIAL_ON

#define PDSTAT0_SERIAL_ON   0x2

Definition at line 346 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT1_CPU_ON

#define PDSTAT1_CPU_ON   0x2

Definition at line 353 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT1_RFC_ON

#define PDSTAT1_RFC_ON   0x4

Definition at line 354 of file cc26x2_cc13x2_prcm.h.

◆ PDSTAT1_VIMS_ON

#define PDSTAT1_VIMS_ON   0x8

Definition at line 355 of file cc26x2_cc13x2_prcm.h.

◆ PRCM

#define PRCM   ((prcm_regs_t *) (PRCM_BASE))

PRCM register bank.

Definition at line 381 of file cc26x2_cc13x2_prcm.h.

◆ PRCM_NONBUF

#define PRCM_NONBUF   ((prcm_regs_t *) (PRCM_BASE_NONBUF))

PRCM register bank (nonbuf)

Definition at line 382 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGDS_CLK_EN_UART0

#define UARTCLKGDS_CLK_EN_UART0   0x1

Definition at line 369 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGDS_CLK_EN_UART1

#define UARTCLKGDS_CLK_EN_UART1   0x2

Definition at line 370 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGR_CLK_EN_UART0

#define UARTCLKGR_CLK_EN_UART0   0x1

Definition at line 359 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGR_CLK_EN_UART1

#define UARTCLKGR_CLK_EN_UART1   0x2

Definition at line 360 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGS_CLK_EN_UART0

#define UARTCLKGS_CLK_EN_UART0   0x1

Definition at line 364 of file cc26x2_cc13x2_prcm.h.

◆ UARTCLKGS_CLK_EN_UART1

#define UARTCLKGS_CLK_EN_UART1   0x2

Definition at line 365 of file cc26x2_cc13x2_prcm.h.

Function Documentation

◆ osc_hf_source_switch()

void osc_hf_source_switch ( uint32_t  osc)

DDI_0_OSC functions.

Switch the high frequency clock.

Note
This function will not return until the clock source has been switched.
Parameters
[in]oscThe oscillator to use.