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periph_conf.h
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1/*
2 * Copyright (C) 2014 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an HSE */
23#ifndef CONFIG_BOARD_HAS_HSE
24#define CONFIG_BOARD_HAS_HSE 1
25#endif
26
27/* The HSE provides a 16MHz clock */
28#ifndef CONFIG_CLOCK_HSE
29#define CONFIG_CLOCK_HSE MHZ(16)
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
43static const dma_conf_t dma_config[] = {
44 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
45 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
46};
47
48#define DMA_0_ISR isr_dma2_stream3
49#define DMA_1_ISR isr_dma2_stream2
50
51#define DMA_NUMOF ARRAY_SIZE(dma_config)
58static const timer_conf_t timer_config[] = {
59 {
60 .dev = TIM2,
61 .max = 0xffffffff,
62 .rcc_mask = RCC_APB1ENR_TIM2EN,
63 .bus = APB1,
64 .irqn = TIM2_IRQn
65 },
66 {
67 .dev = TIM5,
68 .max = 0xffffffff,
69 .rcc_mask = RCC_APB1ENR_TIM5EN,
70 .bus = APB1,
71 .irqn = TIM5_IRQn
72 }
73};
74
75#define TIMER_0_ISR isr_tim2
76#define TIMER_1_ISR isr_tim5
77
78#define TIMER_NUMOF ARRAY_SIZE(timer_config)
85static const pwm_conf_t pwm_config[] = {
86 {
87 .dev = TIM11,
88 .rcc_mask = RCC_APB2ENR_TIM11EN,
89 .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 0 },
90 { .pin = GPIO_UNDEF, .cc_chan = 0 },
91 { .pin = GPIO_UNDEF, .cc_chan = 0 },
92 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
93 .af = GPIO_AF3,
94 .bus = APB2
95 }
96};
97
98#define PWM_NUMOF ARRAY_SIZE(pwm_config)
108static const adc_conf_t adc_config[] = {
109 {GPIO_PIN(PORT_B, 0), 0, 8},
110 {GPIO_PIN(PORT_B, 1), 0, 9},
111 {GPIO_UNDEF, 0, 18}, /* VBAT */
112};
113
114#define VBAT_ADC ADC_LINE(2)
115#define ADC_NUMOF ARRAY_SIZE(adc_config)
122static const dac_conf_t dac_config[] = {
123 { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
124 { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
125};
126
127#define DAC_NUMOF ARRAY_SIZE(dac_config)
134static const uart_conf_t uart_config[] = {
135 {
136 .dev = USART2,
137 .rcc_mask = RCC_APB1ENR_USART2EN,
138 .rx_pin = GPIO_PIN(PORT_A, 3),
139 .tx_pin = GPIO_PIN(PORT_A, 2),
140 .rx_af = GPIO_AF7,
141 .tx_af = GPIO_AF7,
142 .bus = APB1,
143 .irqn = USART2_IRQn,
144#ifdef MODULE_PERIPH_DMA
145 .dma = DMA_STREAM_UNDEF,
146 .dma_chan = UINT8_MAX,
147#endif
148 },
149 {
150 .dev = USART1,
151 .rcc_mask = RCC_APB2ENR_USART1EN,
152 .rx_pin = GPIO_PIN(PORT_A, 10),
153 .tx_pin = GPIO_PIN(PORT_A, 9),
154 .rx_af = GPIO_AF7,
155 .tx_af = GPIO_AF7,
156 .bus = APB2,
157 .irqn = USART1_IRQn,
158#ifdef MODULE_PERIPH_DMA
159 .dma = DMA_STREAM_UNDEF,
160 .dma_chan = UINT8_MAX,
161#endif
162 },
163 {
164 .dev = USART3,
165 .rcc_mask = RCC_APB1ENR_USART3EN,
166 .rx_pin = GPIO_PIN(PORT_D, 9),
167 .tx_pin = GPIO_PIN(PORT_D, 8),
168 .rx_af = GPIO_AF7,
169 .tx_af = GPIO_AF7,
170 .bus = APB1,
171 .irqn = USART3_IRQn,
172#ifdef MODULE_PERIPH_DMA
173 .dma = DMA_STREAM_UNDEF,
174 .dma_chan = UINT8_MAX,
175#endif
176 },
177};
178
179/* assign ISR vector names */
180#define UART_0_ISR (isr_usart2)
181#define UART_1_ISR (isr_usart1)
182#define UART_2_ISR (isr_usart3)
183
184/* deduct number of defined UART interfaces */
185#define UART_NUMOF ARRAY_SIZE(uart_config)
192static const spi_conf_t spi_config[] = {
193 {
194 .dev = SPI1,
195 .mosi_pin = GPIO_PIN(PORT_A, 7),
196 .miso_pin = GPIO_PIN(PORT_A, 6),
197 .sclk_pin = GPIO_PIN(PORT_A, 5),
198 .cs_pin = GPIO_PIN(PORT_A, 4),
199 .mosi_af = GPIO_AF5,
200 .miso_af = GPIO_AF5,
201 .sclk_af = GPIO_AF5,
202 .cs_af = GPIO_AF5,
203 .rccmask = RCC_APB2ENR_SPI1EN,
204 .apbbus = APB2,
205#ifdef MODULE_PERIPH_DMA
206 .tx_dma = 0,
207 .tx_dma_chan = 3,
208 .rx_dma = 1,
209 .rx_dma_chan = 3,
210#endif
211 }
212};
213
214#define SPI_NUMOF ARRAY_SIZE(spi_config)
221static const i2c_conf_t i2c_config[] = {
222 {
223 .dev = I2C1,
224 .speed = I2C_SPEED_NORMAL,
225 .scl_pin = GPIO_PIN(PORT_B, 6),
226 .sda_pin = GPIO_PIN(PORT_B, 7),
227 .scl_af = GPIO_AF4,
228 .sda_af = GPIO_AF4,
229 .bus = APB1,
230 .rcc_mask = RCC_APB1ENR_I2C1EN,
231 .clk = CLOCK_APB1,
232 .irqn = I2C1_EV_IRQn
233 }
234};
235
236#define I2C_0_ISR isr_i2c1_ev
237
238#define I2C_NUMOF ARRAY_SIZE(i2c_config)
241#ifdef __cplusplus
242}
243#endif
244
245#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
DAC line configuration data.
Definition periph_cpu.h:301
gpio_t pin
pin connected to the line
Definition periph_cpu.h:302
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219