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periph_conf.h
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1/*
2 * Copyright (C) 2015 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* HSE available on this board */
23#ifndef CONFIG_BOARD_HAS_HSE
24#define CONFIG_BOARD_HAS_HSE 1
25#endif
26
27/* This board provides an LSE */
28#ifndef CONFIG_BOARD_HAS_LSE
29#define CONFIG_BOARD_HAS_LSE 1
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34#include "cfg_i2c1_pb8_pb9.h"
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
44static const dma_conf_t dma_config[] = {
45 { .stream = 1 },
46 { .stream = 2 },
47};
48
49#define DMA_SHARED_ISR_0 isr_dma1_ch2_3_dma2_ch1_2
50#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
51
52#define DMA_NUMOF ARRAY_SIZE(dma_config)
59static const timer_conf_t timer_config[] = {
60 {
61 .dev = TIM1,
62 .max = 0x0000ffff,
63 .rcc_mask = RCC_APB2ENR_TIM1EN,
64 .bus = APB2,
65 .irqn = TIM1_CC_IRQn
66 }
67};
68
69#define TIMER_0_ISR isr_tim1_cc
70
71#define TIMER_NUMOF ARRAY_SIZE(timer_config)
78static const uart_conf_t uart_config[] = {
79 {
80 .dev = USART2,
81 .rcc_mask = RCC_APB1ENR_USART2EN,
82 .rx_pin = GPIO_PIN(PORT_A, 3),
83 .tx_pin = GPIO_PIN(PORT_A, 2),
84 .rx_af = GPIO_AF1,
85 .tx_af = GPIO_AF1,
86 .bus = APB1,
87 .irqn = USART2_IRQn,
88#ifdef MODULE_PERIPH_DMA
89 .dma = 0,
90 .dma_chan = 0x9,
91#endif
92 },
93 {
94 .dev = USART1,
95 .rcc_mask = RCC_APB2ENR_USART1EN,
96 .rx_pin = GPIO_PIN(PORT_A, 10),
97 .tx_pin = GPIO_PIN(PORT_A, 9),
98 .rx_af = GPIO_AF1,
99 .tx_af = GPIO_AF1,
100 .bus = APB2,
101 .irqn = USART1_IRQn,
102#ifdef MODULE_PERIPH_DMA
103 .dma = 0,
104 .dma_chan = 0x8,
105#endif
106 },
107 {
108 .dev = USART3,
109 .rcc_mask = RCC_APB1ENR_USART3EN,
110 .rx_pin = GPIO_PIN(PORT_C, 11),
111 .tx_pin = GPIO_PIN(PORT_C, 10),
112 .rx_af = GPIO_AF1,
113 .tx_af = GPIO_AF1,
114 .bus = APB1,
115 .irqn = USART3_8_IRQn,
116#ifdef MODULE_PERIPH_DMA
117 .dma = 0,
118 .dma_chan = 0xA,
119#endif
120 },
121};
122
123#define UART_0_ISR (isr_usart2)
124#define UART_1_ISR (isr_usart1)
125#define UART_2_ISR (isr_usart3_8)
126
127#define UART_NUMOF ARRAY_SIZE(uart_config)
134static const spi_conf_t spi_config[] = {
135 {
136 .dev = SPI1,
137 .mosi_pin = GPIO_PIN(PORT_A, 7),
138 .miso_pin = GPIO_PIN(PORT_A, 6),
139 .sclk_pin = GPIO_PIN(PORT_A, 5),
140 .cs_pin = GPIO_PIN(PORT_B, 6),
141 .mosi_af = GPIO_AF0,
142 .miso_af = GPIO_AF0,
143 .sclk_af = GPIO_AF0,
144 .cs_af = GPIO_AF0,
145 .rccmask = RCC_APB2ENR_SPI1EN,
146 .apbbus = APB2,
147#ifdef MODULE_PERIPH_DMA
148 .tx_dma = 1,
149 .tx_dma_chan = 0,
150 .rx_dma = 0,
151 .rx_dma_chan = 0,
152#endif
153 }
154};
155
156#define SPI_NUMOF ARRAY_SIZE(spi_config)
163static const pwm_conf_t pwm_config[] = {
164 {
165 .dev = TIM2,
166 .rcc_mask = RCC_APB1ENR_TIM2EN,
167 .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
168 { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
169 { .pin = GPIO_PIN(PORT_B, 11) , .cc_chan = 3 },
170 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
171 .af = GPIO_AF2,
172 .bus = APB1
173 },
174 {
175 .dev = TIM3,
176 .rcc_mask = RCC_APB1ENR_TIM3EN,
177 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
178 { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
179 { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
180 { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
181 .af = GPIO_AF0,
182 .bus = APB1
183 }
184};
185
186#define PWM_NUMOF ARRAY_SIZE(pwm_config)
193static const adc_conf_t adc_config[] = {
194 { GPIO_PIN(PORT_A, 0), 0 },
195 { GPIO_PIN(PORT_A, 1), 1 },
196 { GPIO_PIN(PORT_A, 4), 4 },
197 { GPIO_PIN(PORT_B, 0), 8 },
198 { GPIO_PIN(PORT_C, 1), 11 },
199 { GPIO_PIN(PORT_C, 0), 10 },
200 { GPIO_UNDEF, 18 }, /* VBAT */
201};
202
203#define VBAT_ADC ADC_LINE(6)
204#define ADC_NUMOF ARRAY_SIZE(adc_config)
207#ifdef __cplusplus
208}
209#endif
210
211#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:102
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
DMA configuration.
Definition cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219