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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-FileCopyrightText: 2015 Freie Universität Berlin
4 * SPDX-FileCopyrightText: 2015 Hamburg University of Applied Sciences
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34#include "cfg_timer_tim2.h"
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
50static const adc_conf_t adc_config[] = {
51 { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 1 }, /* ADC_IN1, fast */
52 { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 2 }, /* ADC_IN2, fast */
53 { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 5 }, /* ADC_IN5, fast */
54 { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 11 }, /* ADC_IN11, slow */
55 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 7 }, /* ADC_IN7, slow */
56 { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 6 }, /* ADC_IN6, slow */
57 { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
58};
59
60#define VBAT_ADC ADC_LINE(6)
61#define ADC_NUMOF ARRAY_SIZE(adc_config)
63
68static const uart_conf_t uart_config[] = {
69 {
70 .dev = USART2,
71 .rcc_mask = RCC_APB1ENR_USART2EN,
72 .rx_pin = GPIO_PIN(PORT_A, 3),
73 .tx_pin = GPIO_PIN(PORT_A, 2),
74 .rx_af = GPIO_AF7,
75 .tx_af = GPIO_AF7,
76 .bus = APB1,
77 .irqn = USART2_IRQn
78 },
79 {
80 .dev = USART1,
81 .rcc_mask = RCC_APB2ENR_USART1EN,
82 .rx_pin = GPIO_PIN(PORT_A, 10),
83 .tx_pin = GPIO_PIN(PORT_A, 9),
84 .rx_af = GPIO_AF7,
85 .tx_af = GPIO_AF7,
86 .bus = APB2,
87 .irqn = USART1_IRQn
88 },
89 {
90 .dev = USART3,
91 .rcc_mask = RCC_APB1ENR_USART3EN,
92 .rx_pin = GPIO_PIN(PORT_C, 11),
93 .tx_pin = GPIO_PIN(PORT_C, 10),
94 .rx_af = GPIO_AF7,
95 .tx_af = GPIO_AF7,
96 .bus = APB1,
97 .irqn = USART3_IRQn
98 }
99};
100
101#define UART_0_ISR (isr_usart2)
102#define UART_1_ISR (isr_usart1)
103#define UART_2_ISR (isr_usart3)
104
105#define UART_NUMOF ARRAY_SIZE(uart_config)
107
112static const pwm_conf_t pwm_config[] = {
113 {
114 .dev = TIM16,
115 .rcc_mask = RCC_APB2ENR_TIM16EN,
116 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
117 { .pin = GPIO_UNDEF, .cc_chan = 0 },
118 { .pin = GPIO_UNDEF, .cc_chan = 0 },
119 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
120 .af = GPIO_AF1,
121 .bus = APB2
122 }
123};
124
125#define PWM_NUMOF ARRAY_SIZE(pwm_config)
127
132static const spi_conf_t spi_config[] = {
133 {
134 .dev = SPI2,
135 .mosi_pin = GPIO_PIN(PORT_B, 15),
136 .miso_pin = GPIO_PIN(PORT_B, 14),
137 .sclk_pin = GPIO_PIN(PORT_B, 13),
138 .cs_pin = GPIO_PIN(PORT_B, 12),
139 .mosi_af = GPIO_AF5,
140 .miso_af = GPIO_AF5,
141 .sclk_af = GPIO_AF5,
142 .cs_af = GPIO_AF5,
143 .rccmask = RCC_APB1ENR_SPI2EN,
144 .apbbus = APB1
145 }
146};
147
148#define SPI_NUMOF ARRAY_SIZE(spi_config)
150
155static const i2c_conf_t i2c_config[] = {
156 {
157 .dev = I2C1,
158 .speed = I2C_SPEED_NORMAL,
159 .scl_pin = GPIO_PIN(PORT_B, 8),
160 .sda_pin = GPIO_PIN(PORT_B, 9),
161 .scl_af = GPIO_AF4,
162 .sda_af = GPIO_AF4,
163 .bus = APB1,
164 .rcc_mask = RCC_APB1ENR_I2C1EN,
165 .rcc_sw_mask = RCC_CFGR3_I2C1SW,
166 .irqn = I2C1_ER_IRQn
167 },
168 {
169 .dev = I2C3,
170 .speed = I2C_SPEED_NORMAL,
171 .scl_pin = GPIO_PIN(PORT_A, 8),
172 .sda_pin = GPIO_PIN(PORT_A, 5),
173 .scl_af = GPIO_AF5,
174 .sda_af = GPIO_AF8,
175 .bus = APB1,
176 .rcc_mask = RCC_APB1ENR_I2C3EN,
177 .rcc_sw_mask = RCC_CFGR3_I2C3SW,
178 .irqn = I2C3_ER_IRQn
179 }
180};
181
182#define I2C_0_ISR isr_i2c1_er
183#define I2C_1_ISR isr_i2c3_er
184
185#define I2C_NUMOF ARRAY_SIZE(i2c_config)
187
188#ifdef __cplusplus
189}
190#endif
191
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
I2C configuration structure.
Definition periph_cpu.h:298
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217