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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_timer_tim2.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
46static const adc_conf_t adc_config[] = {
47 { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 4 }, /* ADC1_IN4, fast */
48 { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 6 }, /* ADC12_IN6, slow */
49 { .pin = GPIO_PIN(PORT_C, 3), .dev = 1, .chan = 9 }, /* ADC12_IN9, slow */
50 { .pin = GPIO_PIN(PORT_D, 11), .dev = 2, .chan = 8 }, /* ADC34_IN8, slow */
51 { .pin = GPIO_PIN(PORT_D, 12), .dev = 3, .chan = 9 }, /* ADC34_IN9, slow */
52 { .pin = GPIO_PIN(PORT_D, 13), .dev = 3, .chan = 10 }, /* ADC34_IN10, slow */
53 { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
54};
55
56#define VBAT_ADC ADC_LINE(6)
57#define ADC_NUMOF ARRAY_SIZE(adc_config)
59
64static const uart_conf_t uart_config[] = {
65 {
66 .dev = USART3,
67 .rcc_mask = RCC_APB1ENR_USART3EN,
68 .rx_pin = GPIO_PIN(PORT_D, 9),
69 .tx_pin = GPIO_PIN(PORT_D, 8),
70 .rx_af = GPIO_AF7,
71 .tx_af = GPIO_AF7,
72 .bus = APB1,
73 .irqn = USART3_IRQn,
74#ifdef UART_USE_DMA
75 .dma_stream = 6,
76 .dma_chan = 4
77#endif
78 },
79 {
80 .dev = USART1,
81 .rcc_mask = RCC_APB2ENR_USART1EN,
82 .rx_pin = GPIO_PIN(PORT_C, 5),
83 .tx_pin = GPIO_PIN(PORT_C, 4),
84 .rx_af = GPIO_AF7,
85 .tx_af = GPIO_AF7,
86 .bus = APB2,
87 .irqn = USART1_IRQn,
88#ifdef UART_USE_DMA
89 .dma_stream = 5,
90 .dma_chan = 4
91#endif
92 },
93 {
94 .dev = USART2,
95 .rcc_mask = RCC_APB1ENR_USART2EN,
96 .rx_pin = GPIO_PIN(PORT_D, 6),
97 .tx_pin = GPIO_PIN(PORT_D, 5),
98 .rx_af = GPIO_AF7,
99 .tx_af = GPIO_AF7,
100 .bus = APB1,
101 .irqn = USART2_IRQn,
102#ifdef UART_USE_DMA
103 .dma_stream = 4,
104 .dma_chan = 4
105#endif
106 },
107};
108
109#define UART_0_ISR (isr_usart3)
110#define UART_0_DMA_ISR (isr_dma1_stream6)
111#define UART_1_ISR (isr_usart1)
112#define UART_1_DMA_ISR (isr_dma1_stream5)
113#define UART_2_ISR (isr_usart2)
114#define UART_2_DMA_ISR (isr_dma1_stream4)
115
116#define UART_NUMOF ARRAY_SIZE(uart_config)
118
123static const pwm_conf_t pwm_config[] = {
124 {
125 .dev = TIM1,
126 .rcc_mask = RCC_APB2ENR_TIM1EN,
127 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
128 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
129 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
130 { .pin = GPIO_UNDEF, .cc_chan = 0} },
131 .af = GPIO_AF2,
132 .bus = APB2
133 },
134 {
135 .dev = TIM4,
136 .rcc_mask = RCC_APB1ENR_TIM4EN,
137 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
138 { .pin = GPIO_UNDEF, .cc_chan = 0},
139 { .pin = GPIO_UNDEF, .cc_chan = 0},
140 { .pin = GPIO_UNDEF, .cc_chan = 0} },
141 .af = GPIO_AF2,
142 .bus = APB1
143 }
144};
145
146#define PWM_NUMOF ARRAY_SIZE(pwm_config)
148
153static const spi_conf_t spi_config[] = {
154 {
155 .dev = SPI1,
156 .mosi_pin = GPIO_PIN(PORT_A, 7),
157 .miso_pin = GPIO_PIN(PORT_A, 6),
158 .sclk_pin = GPIO_PIN(PORT_A, 5),
159 .cs_pin = SPI_CS_UNDEF,
160 .mosi_af = GPIO_AF5,
161 .miso_af = GPIO_AF5,
162 .sclk_af = GPIO_AF5,
163 .cs_af = GPIO_AF5,
164 .rccmask = RCC_APB2ENR_SPI1EN,
165 .apbbus = APB2
166 }
167};
168
169#define SPI_NUMOF ARRAY_SIZE(spi_config)
171
176 {
177 .base_addr = (uintptr_t)USB,
178 .rcc_mask = RCC_APB1ENR_USBEN,
179 .irqn = USB_LP_CAN_RX0_IRQn,
180 .apb = APB1,
181 .dm = GPIO_PIN(PORT_A, 11),
182 .dp = GPIO_PIN(PORT_A, 12),
183 .af = GPIO_AF14,
184 .disconn = GPIO_PIN(PORT_G, 6),
185 },
186};
187
191#define USBDEV_ISR isr_usb_lp_can_rx0
192
196#define USBDEV_NUMOF ARRAY_SIZE(stm32_usbdev_fs_config)
197
198#ifdef __cplusplus
199}
200#endif
201
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const stm32_usbdev_fs_config_t stm32_usbdev_fs_config[]
USB device FS configuration.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF14
use alternate function 14
Definition cpu_gpio.h:116
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
stm32 USB device FS configuration
Definition cpu_usbdev.h:44
UART device configuration.
Definition periph_cpu.h:217