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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
31#include "cfg_rtt_default.h"
32#include "cfg_timer_tim2.h"
33#include "cfg_usb_otg_fs.h"
34#include "mii.h"
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
44static const dma_conf_t dma_config[] = {
45 { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
46 { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
47 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
48 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
49 { .stream = 13 }, /* DMA2 Stream 5 - SPI1_TX */
50 { .stream = 11 }, /* DMA2 Stream 3 - SPI4_RX */
51 { .stream = 12 }, /* DMA2 Stream 4 - SPI4_TX */
52 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
53};
54
55#define DMA_0_ISR isr_dma1_stream4
56#define DMA_1_ISR isr_dma2_stream6
57#define DMA_2_ISR isr_dma1_stream6
58
59#define DMA_3_ISR isr_dma2_stream2
60#define DMA_4_ISR isr_dma2_stream5
61#define DMA_5_ISR isr_dma2_stream3
62#define DMA_6_ISR isr_dma2_stream4
63
64#define DMA_7_ISR isr_dma2_stream0
65
66#define DMA_NUMOF ARRAY_SIZE(dma_config)
68
73static const pwm_conf_t pwm_config[] = {
74 {
75 .dev = TIM1,
76 .rcc_mask = RCC_APB2ENR_TIM1EN,
77 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 CN10-4 */, .cc_chan = 0},
78 { .pin = GPIO_PIN(PORT_E, 11) /* D5 CN10-6 */, .cc_chan = 1},
79 { .pin = GPIO_PIN(PORT_E, 13) /* D3 CN10-10 */, .cc_chan = 2},
80 { .pin = GPIO_PIN(PORT_E, 14) /* D38 CN10-28 */, .cc_chan = 3} },
81 .af = GPIO_AF1,
82 .bus = APB2
83 },
84 {
85 .dev = TIM4,
86 .rcc_mask = RCC_APB1ENR_TIM4EN,
87 .chan = { { .pin = GPIO_PIN(PORT_D, 12) /* D29 CN10-21 */, .cc_chan = 0},
88 { .pin = GPIO_PIN(PORT_D, 13) /* D28 CN10-19 */, .cc_chan = 1},
89 { .pin = GPIO_PIN(PORT_D, 14) /* D10 CN7-16 */, .cc_chan = 2},
90 { .pin = GPIO_PIN(PORT_D, 15) /* D9 CN7-18 */, .cc_chan = 3} },
91 .af = GPIO_AF2,
92 .bus = APB1
93 },
94};
95
96#define PWM_NUMOF ARRAY_SIZE(pwm_config)
98
103static const uart_conf_t uart_config[] = {
104 {
105 .dev = USART3,
106 .rcc_mask = RCC_APB1ENR_USART3EN,
107 .rx_pin = GPIO_PIN(PORT_D, 9),
108 .tx_pin = GPIO_PIN(PORT_D, 8),
109 .rx_af = GPIO_AF7,
110 .tx_af = GPIO_AF7,
111 .bus = APB1,
112 .irqn = USART3_IRQn,
113#ifdef MODULE_PERIPH_DMA
114 .dma = 0,
115 .dma_chan = 7
116#endif
117 },
118 {
119 .dev = USART6,
120 .rcc_mask = RCC_APB2ENR_USART6EN,
121 .rx_pin = GPIO_PIN(PORT_G, 9),
122 .tx_pin = GPIO_PIN(PORT_G, 14),
123 .rx_af = GPIO_AF8,
124 .tx_af = GPIO_AF8,
125 .bus = APB2,
126 .irqn = USART6_IRQn,
127#ifdef MODULE_PERIPH_DMA
128 .dma = 1,
129 .dma_chan = 5
130#endif
131 },
132 {
133 .dev = USART2,
134 .rcc_mask = RCC_APB1ENR_USART2EN,
135 .rx_pin = GPIO_PIN(PORT_D, 6),
136 .tx_pin = GPIO_PIN(PORT_D, 5),
137 .rx_af = GPIO_AF7,
138 .tx_af = GPIO_AF7,
139 .bus = APB1,
140 .irqn = USART2_IRQn,
141#ifdef MODULE_PERIPH_DMA
142 .dma = 2,
143 .dma_chan = 4
144#endif
145 }
146};
147
148#define UART_0_ISR (isr_usart3)
149#define UART_1_ISR (isr_usart6)
150#define UART_2_ISR (isr_usart2)
151
152#define UART_NUMOF ARRAY_SIZE(uart_config)
154
159static const spi_conf_t spi_config[] = {
160 {
161 .dev = SPI1,
162 /* PA7 is the default MOSI pin, as it is required for compatibility with
163 * Arduino(ish) shields. Sadly, it is also connected to the RMII_DV of
164 * Ethernet PHY. We work around this by remapping the MOSI to PB5 when
165 * the on-board Ethernet PHY is used.
166 */
167#ifdef MODULE_PERIPH_ETH
168 .mosi_pin = GPIO_PIN(PORT_B, 5),
169#else
170 .mosi_pin = GPIO_PIN(PORT_A, 7),
171#endif
172 .miso_pin = GPIO_PIN(PORT_A, 6),
173 .sclk_pin = GPIO_PIN(PORT_A, 5),
174 .cs_pin = SPI_CS_UNDEF,
175 .mosi_af = GPIO_AF5,
176 .miso_af = GPIO_AF5,
177 .sclk_af = GPIO_AF5,
178 .cs_af = GPIO_AF5,
179 .rccmask = RCC_APB2ENR_SPI1EN,
180 .apbbus = APB2,
181#ifdef MODULE_PERIPH_DMA
182 .tx_dma = 4,
183 .tx_dma_chan = 3,
184 .rx_dma = 3,
185 .rx_dma_chan = 3,
186#endif
187 },
188 {
189 .dev = SPI4,
190 .mosi_pin = GPIO_PIN(PORT_E, 6),
191 .miso_pin = GPIO_PIN(PORT_E, 5),
192 .sclk_pin = GPIO_PIN(PORT_E, 2),
193 .cs_pin = SPI_CS_UNDEF,
194 .mosi_af = GPIO_AF5,
195 .miso_af = GPIO_AF5,
196 .sclk_af = GPIO_AF5,
197 .cs_af = GPIO_AF5,
198 .rccmask = RCC_APB2ENR_SPI4EN,
199 .apbbus = APB2,
200#ifdef MODULE_PERIPH_DMA
201 .tx_dma = 6,
202 .tx_dma_chan = 5,
203 .rx_dma = 5,
204 .rx_dma_chan = 5,
205#endif
206 }
207};
208
209#define SPI_NUMOF ARRAY_SIZE(spi_config)
211
216static const eth_conf_t eth_config = {
217 .mode = RMII,
219 .dma = 7,
220 .dma_chan = 8,
221 .phy_addr = 0x00,
222 .pins = {
223 GPIO_PIN(PORT_G, 13),
224 GPIO_PIN(PORT_B, 13),
225 GPIO_PIN(PORT_G, 11),
226 GPIO_PIN(PORT_C, 4),
227 GPIO_PIN(PORT_C, 5),
228 GPIO_PIN(PORT_A, 7),
229 GPIO_PIN(PORT_C, 1),
230 GPIO_PIN(PORT_A, 2),
231 GPIO_PIN(PORT_A, 1),
232 }
233};
234
235#define ETH_DMA_ISR isr_dma2_stream0
236
238
239#ifdef __cplusplus
240}
241#endif
242
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:36
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:68
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:72
Interface definition for MII/RMII h.
DMA configuration.
Definition cpu_dma.h:31
Ethernet Peripheral configuration.
Definition cpu_eth.h:43
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217