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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20/* Add specific clock configuration (HSE, LSE) for this board here */
21#ifndef CONFIG_BOARD_HAS_LSE
22#define CONFIG_BOARD_HAS_LSE 1
23#endif
24
25#include "periph_cpu.h"
26#include "clk_conf.h"
27#include "cfg_i2c1_pb6_pb7.h"
28#include "cfg_rtt_default.h"
29#include "cfg_timer_tim2.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
39static const uart_conf_t uart_config[] = {
40 {
41 .dev = USART2,
42 .rcc_mask = RCC_APB1ENR_USART2EN,
43 .rx_pin = GPIO_PIN(PORT_A, 15),
44 .tx_pin = GPIO_PIN(PORT_A, 2),
45 .rx_af = GPIO_AF4,
46 .tx_af = GPIO_AF4,
47 .bus = APB1,
48 .irqn = USART2_IRQn,
49 .type = STM32_USART,
50 .clk_src = 0, /* Use APB clock */
51 }
52};
53
54#define UART_0_ISR (isr_usart2)
55
56#define UART_NUMOF ARRAY_SIZE(uart_config)
58
63static const pwm_conf_t pwm_config[] = {
64 {
65 .dev = TIM21,
66 .rcc_mask = RCC_APB2ENR_TIM21EN,
67 .chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 },
68 { .pin = GPIO_UNDEF, .cc_chan = 0 },
69 { .pin = GPIO_UNDEF, .cc_chan = 0 },
70 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
71 .af = GPIO_AF5,
72 .bus = APB2
73 }
74};
75
76#define PWM_NUMOF ARRAY_SIZE(pwm_config)
78
83static const spi_conf_t spi_config[] = {
84 {
85 .dev = SPI1,
86 .mosi_pin = GPIO_PIN(PORT_B, 5),
87 .miso_pin = GPIO_PIN(PORT_B, 4),
88 .sclk_pin = GPIO_PIN(PORT_B, 3),
89 .cs_pin = SPI_CS_UNDEF,
90 .mosi_af = GPIO_AF0,
91 .miso_af = GPIO_AF0,
92 .sclk_af = GPIO_AF0,
93 .cs_af = GPIO_AF0,
94 .rccmask = RCC_APB2ENR_SPI1EN,
95 .apbbus = APB2
96 }
97};
98
99#define SPI_NUMOF ARRAY_SIZE(spi_config)
101
106static const adc_conf_t adc_config[] = {
107 { GPIO_PIN(PORT_A, 0), 0 }, /* Pin A0 */
108 { GPIO_PIN(PORT_A, 1), 1 }, /* Pin A1 */
109 { GPIO_PIN(PORT_A, 3), 3 }, /* Pin A2 */
110 { GPIO_PIN(PORT_A, 4), 4 }, /* Pin A3 */
111 { GPIO_PIN(PORT_A, 5), 5 }, /* Pin A4 */
112 { GPIO_PIN(PORT_A, 6), 6 }, /* Pin A5 */
113 { GPIO_PIN(PORT_A, 7), 7 }, /* Pin A6 */
114};
115
116#define ADC_NUMOF ARRAY_SIZE(adc_config)
118
119#ifdef __cplusplus
120}
121#endif
122
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217