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periph_conf.h
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1/*
2 * Copyright (C) 2017 Freie Universität Berlin
3 * 2017 Inria
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CONF_H
22#define PERIPH_CONF_H
23
24/* Add specific clock configuration (HSE, LSE) for this board here */
25#ifndef CONFIG_BOARD_HAS_LSE
26#define CONFIG_BOARD_HAS_LSE 1
27#endif
28
29#include "periph_cpu.h"
30#include "clk_conf.h"
31#include "cfg_rtt_default.h"
32#include "cfg_timer_tim2.h"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
42static const uart_conf_t uart_config[] = {
43 {
44 .dev = USART2,
45 .rcc_mask = RCC_APB1ENR_USART2EN,
46 .rx_pin = GPIO_PIN(PORT_A, 3),
47 .tx_pin = GPIO_PIN(PORT_A, 2),
48 .rx_af = GPIO_AF4,
49 .tx_af = GPIO_AF4,
50 .bus = APB1,
51 .irqn = USART2_IRQn,
52 .type = STM32_USART,
53 .clk_src = 0, /* Use APB clock */
54 },
55 {
56 .dev = USART1,
57 .rcc_mask = RCC_APB2ENR_USART1EN,
58 .rx_pin = GPIO_PIN(PORT_A, 10),
59 .tx_pin = GPIO_PIN(PORT_A, 9),
60 .rx_af = GPIO_AF4,
61 .tx_af = GPIO_AF4,
62 .bus = APB2,
63 .irqn = USART1_IRQn,
64 .type = STM32_USART,
65 .clk_src = 0, /* Use APB clock */
66 },
67#ifdef MODULE_PERIPH_LPUART
68 {
69 .dev = LPUART1,
70 .rcc_mask = RCC_APB1ENR_LPUART1EN,
71 .rx_pin = GPIO_PIN(PORT_C, 11),
72 .tx_pin = GPIO_PIN(PORT_C, 10),
73 .rx_af = GPIO_AF0,
74 .tx_af = GPIO_AF0,
75 .bus = APB1,
76 .irqn = LPUART1_IRQn,
77 .type = STM32_LPUART,
78 .clk_src = 0, /* Use APB clock */
79 },
80#endif
81};
82
83#define UART_0_ISR (isr_usart2)
84#define UART_1_ISR (isr_usart1)
85
86#ifdef MODULE_PERIPH_LPUART
87#define UART_2_ISR (isr_rng_lpuart1)
88#endif
89
90#define UART_NUMOF ARRAY_SIZE(uart_config)
97static const pwm_conf_t pwm_config[] = {
98 {
99 .dev = TIM3,
100 .rcc_mask = RCC_APB1ENR_TIM3EN,
101 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
102 { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
103 { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
104 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
105 .af = GPIO_AF2,
106 .bus = APB1
107 }
108};
109
110#define PWM_NUMOF ARRAY_SIZE(pwm_config)
117static const spi_conf_t spi_config[] = {
118 {
119 .dev = SPI1,
120 .mosi_pin = GPIO_PIN(PORT_A, 7),
121 .miso_pin = GPIO_PIN(PORT_A, 6),
122 .sclk_pin = GPIO_PIN(PORT_A, 5),
123 .cs_pin = SPI_CS_UNDEF,
124 .mosi_af = GPIO_AF0,
125 .miso_af = GPIO_AF0,
126 .sclk_af = GPIO_AF0,
127 .cs_af = GPIO_AF0,
128 .rccmask = RCC_APB2ENR_SPI1EN,
129 .apbbus = APB2
130 }
131};
132
133#define SPI_NUMOF ARRAY_SIZE(spi_config)
140static const adc_conf_t adc_config[] = {
141 { GPIO_PIN(PORT_A, 0), 0 },
142 { GPIO_PIN(PORT_A, 1), 1 },
143 { GPIO_PIN(PORT_A, 4), 4 },
144 { GPIO_PIN(PORT_B, 0), 8 },
145 { GPIO_PIN(PORT_C, 1), 11 },
146 { GPIO_PIN(PORT_C, 0), 10 }
147};
148
149#define ADC_NUMOF ARRAY_SIZE(adc_config)
156static const i2c_conf_t i2c_config[] = {
157 {
158 .dev = I2C1,
159 .speed = I2C_SPEED_NORMAL,
160 .scl_pin = GPIO_PIN(PORT_B, 8),
161 .sda_pin = GPIO_PIN(PORT_B, 9),
162 .scl_af = GPIO_AF4,
163 .sda_af = GPIO_AF4,
164 .bus = APB1,
165 .rcc_mask = RCC_APB1ENR_I2C1EN,
166 .irqn = I2C1_IRQn
167 },
168 {
169 .dev = I2C2,
170 .speed = I2C_SPEED_NORMAL,
171 .scl_pin = GPIO_PIN(PORT_B, 13),
172 .sda_pin = GPIO_PIN(PORT_B, 14),
173 .scl_af = GPIO_AF5,
174 .sda_af = GPIO_AF5,
175 .bus = APB1,
176 .rcc_mask = RCC_APB1ENR_I2C2EN,
177 .irqn = I2C2_IRQn
178 }
179};
180
181#define I2C_0_ISR isr_i2c1
182#define I2C_1_ISR isr_i2c2
183
184#define I2C_NUMOF ARRAY_SIZE(i2c_config)
187#ifdef __cplusplus
188}
189#endif
190
191#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:102
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:39
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
ADC device configuration.
Definition periph_cpu.h:379
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219