Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2019 twostairs
3 * SPDX-FileCopyrightText: 2017 Inria
4 * SPDX-FileCopyrightText: 2017 OTA keys
5 * SPDX-License-Identifier: LGPL-2.1-only
6 */
7
8#pragma once
9
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_i2c1_pb6_pb7.h"
30#include "cfg_timer_tim2.h"
31#include "cfg_rtt_default.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
41static const uart_conf_t uart_config[] = {
42 {
43 .dev = USART2,
44 .rcc_mask = RCC_APB1ENR1_USART2EN,
45 .rx_pin = GPIO_PIN(PORT_A, 15),
46 .tx_pin = GPIO_PIN(PORT_A, 2),
47 .rx_af = GPIO_AF3,
48 .tx_af = GPIO_AF7,
49 .bus = APB1,
50 .irqn = USART2_IRQn,
51 .type = STM32_USART,
52 .clk_src = 0, /* Use APB clock */
53 },
54 {
55 .dev = USART1,
56 .rcc_mask = RCC_APB2ENR_USART1EN,
57 .rx_pin = GPIO_PIN(PORT_A, 10),
58 .tx_pin = GPIO_PIN(PORT_A, 9),
59 .rx_af = GPIO_AF7,
60 .tx_af = GPIO_AF7,
61 .bus = APB2,
62 .irqn = USART1_IRQn,
63 .type = STM32_USART,
64 .clk_src = 0, /* Use APB clock */
65 },
66};
67
68#define UART_0_ISR (isr_usart2)
69#define UART_1_ISR (isr_usart1)
70
71#define UART_NUMOF ARRAY_SIZE(uart_config)
73
78static const pwm_conf_t pwm_config[] = {
79 {
80 .dev = TIM1,
81 .rcc_mask = RCC_APB2ENR_TIM1EN,
82 .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
83 { .pin = GPIO_UNDEF, .cc_chan = 0 },
84 { .pin = GPIO_UNDEF, .cc_chan = 0 },
85 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
86 .af = GPIO_AF1,
87 .bus = APB2
88 }
89};
90
91#define PWM_NUMOF ARRAY_SIZE(pwm_config)
93
98static const spi_conf_t spi_config[] = {
99 {
100 .dev = SPI1,
101 .mosi_pin = GPIO_PIN(PORT_B, 5),
102 .miso_pin = GPIO_PIN(PORT_B, 4),
103 .sclk_pin = GPIO_PIN(PORT_B, 3),
104 .cs_pin = SPI_CS_UNDEF,
105 .mosi_af = GPIO_AF5,
106 .miso_af = GPIO_AF5,
107 .sclk_af = GPIO_AF5,
108 .cs_af = GPIO_AF5,
109 .rccmask = RCC_APB2ENR_SPI1EN,
110 .apbbus = APB2
111 }
112};
113
114#define SPI_NUMOF ARRAY_SIZE(spi_config)
116
148static const adc_conf_t adc_config[] = {
149 {GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 5}, /* ADC1_IN5 */
150 {GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6}, /* ADC1_IN6 */
151 {GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 8}, /* ADC1_IN8 */
152 {GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9}, /* ADC1_IN9 */
153 {GPIO_PIN(PORT_A, 7), .dev = 0, .chan = 12}, /* ADC1_IN12 */
154 {GPIO_UNDEF, .dev = 0, .chan = 18}, /* VBAT */
155};
156
160#define ADC_NUMOF ARRAY_SIZE(adc_config)
161
162#define VBAT_ADC ADC_LINE(5)
163
165
166#ifdef __cplusplus
167}
168#endif
169
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:104
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217