periph_cpu.h

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/*
 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include <limits.h>
 
#include "cpu.h"
#include "macros/units.h"
 
#if defined(CPU_FAM_STM32F0)
#include "periph/f0/periph_cpu.h"
#elif defined(CPU_FAM_STM32F1)
#include "periph/f1/periph_cpu.h"
#elif defined(CPU_FAM_STM32F2)
#include "periph/f2/periph_cpu.h"
#elif defined(CPU_FAM_STM32F3)
#include "periph/f3/periph_cpu.h"
#elif defined(CPU_FAM_STM32F4)
#include "periph/f4/periph_cpu.h"
#elif defined(CPU_FAM_STM32F7)
#include "periph/f7/periph_cpu.h"
#elif defined(CPU_FAM_STM32G0)
#include "periph/g0/periph_cpu.h"
#elif defined(CPU_FAM_STM32C0)
#include "periph/c0/periph_cpu.h"
#elif defined(CPU_FAM_STM32G4)
#include "periph/g4/periph_cpu.h"
#elif defined(CPU_FAM_STM32L0)
#include "periph/l0/periph_cpu.h"
#elif defined(CPU_FAM_STM32L1)
#include "periph/l1/periph_cpu.h"
#elif defined(CPU_FAM_STM32L4)
#include "periph/l4/periph_cpu.h"
#elif defined(CPU_FAM_STM32L5)
#include "periph/l5/periph_cpu.h"
#elif defined(CPU_FAM_STM32U5)
#include "periph/u5/periph_cpu.h"
#elif defined(CPU_FAM_STM32WB)
#include "periph/wb/periph_cpu.h"
#elif defined(CPU_FAM_STM32WL)
#include "periph/wl/periph_cpu.h"
#endif
 
#include "periph/cpu_backup_ram.h"
#include "periph/cpu_common.h"
#include "periph/cpu_dma.h"
#include "periph/cpu_eth.h"
#include "periph/cpu_fmc.h"
#include "periph/cpu_gpio.h"
#include "periph/cpu_gpio_ll.h"
#include "periph/cpu_i2c.h"
#include "periph/cpu_ltdc.h"
#include "periph/cpu_pm.h"
#include "periph/cpu_pwm.h"
#include "periph/cpu_qdec.h"
#include "periph/cpu_sdmmc.h"
#include "periph/cpu_spi.h"
#include "periph/cpu_timer.h"
#include "periph/cpu_uart.h"
#include "periph/cpu_usbdev.h"
#include "periph/cpu_vbat.h"
#include "periph/cpu_wdt.h"
 
#ifdef MODULE_PERIPH_CAN
#ifdef MODULE_FDCAN
#include "fdcandev_stm32.h"
#else
#include "candev_stm32.h"
#endif
#endif
 
#ifdef __cplusplus
extern "C" {
#endif

typedef struct {
    gpio_t pin;             
#if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
    !defined(CPU_FAM_STM32L1) && !defined(CPU_FAM_STM32WL)
    uint8_t dev;            
#endif
    uint8_t chan;           
} adc_conf_t;

typedef struct {
    gpio_t pin;             
    uint8_t chan;           
} dac_conf_t;

#define HAVE_PTP_CLOCK_READ         1   
#define HAVE_PTP_CLOCK_SET          1   
#define HAVE_PTP_TIMER_SET_ABSOLUTE 1   
 
#if !DOXYGEN    /* hide implementation details */
/* Detect the IP version based on the available register define */
#if defined(USB_OTG_GCCFG_NOVBUSSENS)
#define STM32_USB_OTG_CID_1x        
#elif defined(USB_OTG_GCCFG_VBDEN)
#define STM32_USB_OTG_CID_2x        
#elif defined(USB)
#define STM32_USB_FS_CID_1x         
#endif

#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS)
#define STM32_USB_OTG_FS_NUM_EP     (USB_OTG_FS_MAX_IN_ENDPOINTS)
#elif defined(STM32_USB_OTG_CID_1x)
#define STM32_USB_OTG_FS_NUM_EP     (4)    
#elif defined(STM32_USB_OTG_CID_2x)
#define STM32_USB_OTG_FS_NUM_EP     (6)    
#endif

#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS)
#define STM32_USB_OTG_HS_NUM_EP     (USB_OTG_HS_MAX_IN_ENDPOINTS)
#elif defined(STM32_USB_OTG_CID_1x)
#define STM32_USB_OTG_HS_NUM_EP     (6)     
#elif defined(STM32_USB_OTG_CID_2x)
#define STM32_USB_OTG_HS_NUM_EP     (9)     
#endif

#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP)
#define USBDEV_NUM_ENDPOINTS            STM32_USB_OTG_HS_NUM_EP
#elif defined(STM32_USB_OTG_FS_NUM_EP)
#define USBDEV_NUM_ENDPOINTS            STM32_USB_OTG_FS_NUM_EP
#else
#define USBDEV_NUM_ENDPOINTS            8
#endif
 
/* unify names across STM32 families */
#ifdef SPI_CR1_CPHA_Msk
#  define STM32_SPI_CPHA_Msk            SPI_CR1_CPHA_Msk
#endif
#ifdef SPI_CFG2_CPHA_Msk
#  define STM32_SPI_CPHA_Msk            SPI_CFG2_CPHA_Msk
#endif
#ifdef SPI_CR1_CPOL_Msk
#  define STM32_SPI_CPOL_Msk            SPI_CR1_CPOL_Msk
#endif
#ifdef SPI_CFG2_CPOL_Msk
#  define STM32_SPI_CPOL_Msk            SPI_CFG2_CPOL_Msk
#endif

#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = 0,                                         
    SPI_MODE_1 = STM32_SPI_CPHA_Msk,                        
    SPI_MODE_2 = STM32_SPI_CPOL_Msk,                        
    SPI_MODE_3 = STM32_SPI_CPOL_Msk | STM32_SPI_CPHA_Msk,   
} spi_mode_t;
 
#endif /* !DOXYGEN */
 
#ifdef __cplusplus
}
#endif