periph_cpu.h File Reference

STM32F1 CPU specific definitions for internal peripheral handling. More...

Detailed Description

STM32F1 CPU specific definitions for internal peripheral handling.

Author

Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

Definition in file periph_cpu.h.

#include "cpu_conf.h"

Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Macros
#define	ADC_DEVS   (2U)
	Available number of ADC devices.
#define	CONFIG_AFIO_MAPR_SWJ_CFG   SWJ_CFG_NO_JTAG_DP
	By default, disable JTAG and keep only SWD.

Enumerations
enum	afio_mapr_swj_cfg_t { SWJ_CFG_FULL_SWJ = 0 , SWJ_CFG_NO_NJTRST = AFIO_MAPR_SWJ_CFG_NOJNTRST , SWJ_CFG_NO_JTAG_DP = AFIO_MAPR_SWJ_CFG_JTAGDISABLE , SWJ_CFG_DISABLED = AFIO_MAPR_SWJ_CFG_DISABLE }
	Possible values of the SWJ_CFG field in the AFIO->MAPR register. More...

Functions
static uint32_t	afio_mapr_read (void)
	Read the current value of the AFIO->MAPR register reproducibly.
static void	afio_mapr_write (uint32_t new_value)
	Write to the AFIO->MAPR register apply the SWJ configuration specified via CONFIG_AFIO_MAPR_SWJ_CFG.

Real time counter configuration
#define	RTT_IRQ_PRIO   1
#define	RTT_DEV   RTC
#define	RTT_IRQ   RTC_IRQn
#define	RTT_ISR   isr_rtc
#define	RTT_MAX_VALUE   (0xffffffff)
#define	RTT_CLOCK_FREQUENCY   (32768U) /* in Hz */
#define	RTT_MIN_FREQUENCY   (1U) /* in Hz */
#define	RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY / 2) /* in Hz */

GPIO Definitions Missing in Vendor Files
enum	{ GPIO_CRL_MODE0_INPUT = (0x0 << GPIO_CRL_MODE0_Pos) , GPIO_CRL_MODE0_OUTPUT_10MHZ = (0x1 << GPIO_CRL_MODE0_Pos) , GPIO_CRL_MODE0_OUTPUT_2MHZ = (0x2 << GPIO_CRL_MODE0_Pos) , GPIO_CRL_MODE0_OUTPUT_50MHZ = (0x3 << GPIO_CRL_MODE0_Pos) }
	Possible values of the MODE0 field in the GPIO CRL register. More...
enum	{   GPIO_CRL_CNF0_INPUT_ANALOG = (0x0 << GPIO_CRL_CNF0_Pos) , GPIO_CRL_CNF0_INPUT_FLOATING = (0x1 << GPIO_CRL_CNF0_Pos) , GPIO_CRL_CNF0_INPUT_PULL = (0x2 << GPIO_CRL_CNF0_Pos) , GPIO_CRL_CNF0_OUTPUT_PUSH_PULL = (0x0 << GPIO_CRL_CNF0_Pos) ,   GPIO_CRL_CNF0_OUTPUT_OPEN_DRAIN = (0x1 << GPIO_CRL_CNF0_Pos) , GPIO_CRL_CNF0_AF_PUSH_PULL = (0x2 << GPIO_CRL_CNF0_Pos) , GPIO_CRL_CNF0_AF_OPEN_DRAIN = (0x3 << GPIO_CRL_CNF0_Pos) }
	Possible values of the CNF0 field in the GPIO CRL register. More...

Macro Definition Documentation

ADC_DEVS

#define ADC_DEVS   (2U)

Available number of ADC devices.

Definition at line 66 of file periph_cpu.h.

CONFIG_AFIO_MAPR_SWJ_CFG

#define CONFIG_AFIO_MAPR_SWJ_CFG   SWJ_CFG_NO_JTAG_DP

By default, disable JTAG and keep only SWD.

This frees the JTAG pins for use as regular GPIOs. We do not support flashing or debugging via JTAG anyway, so there is nothing lost except for a few bytes of ROM to initialize the SWJ_CFG register.

Definition at line 145 of file periph_cpu.h.

RTT_CLOCK_FREQUENCY

#define RTT_CLOCK_FREQUENCY   (32768U) /* in Hz */

Definition at line 57 of file periph_cpu.h.

RTT_DEV

#define RTT_DEV   RTC

Definition at line 52 of file periph_cpu.h.

RTT_IRQ

#define RTT_IRQ   RTC_IRQn

Definition at line 53 of file periph_cpu.h.

RTT_IRQ_PRIO

#define RTT_IRQ_PRIO   1

Definition at line 50 of file periph_cpu.h.

RTT_ISR

#define RTT_ISR   isr_rtc

Definition at line 54 of file periph_cpu.h.

RTT_MAX_FREQUENCY

#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY / 2) /* in Hz */

Definition at line 60 of file periph_cpu.h.

RTT_MAX_VALUE

#define RTT_MAX_VALUE   (0xffffffff)

Definition at line 56 of file periph_cpu.h.

RTT_MIN_FREQUENCY

#define RTT_MIN_FREQUENCY   (1U) /* in Hz */

Definition at line 58 of file periph_cpu.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Possible values of the MODE0 field in the GPIO CRL register.

The MODE1 to MODE7 fields have the same values. Don't forget to shift the constants to the field position for MODE1 to MODE7 by 4 times n bits, where n is the pin number.

In addition the MODE8 to MODE15 fields in the CRH register have the same layout and semantics as the MODE0 to MODE 7 fields in the CRL register.

Definition at line 82 of file periph_cpu.h.

anonymous enum

anonymous enum

Possible values of the CNF0 field in the GPIO CRL register.

The CNF1 to CNF7 fields have the same values. Don't forget to shift the constants to the field position for CNF1 to CNF7 by 4 times n bits, where n is the pin number.

In addition the CNF8 to CNF15 fields in the CRH register have the same layout and semantics as the CNF0 to CNF 7 fields in the CRL register.

Definition at line 99 of file periph_cpu.h.

afio_mapr_swj_cfg_t

enum afio_mapr_swj_cfg_t

Possible values of the SWJ_CFG field in the AFIO->MAPR register.

This wraps the vendor header file preprocessor macros into a C language enum.

Enumerator
SWJ_CFG_FULL_SWJ	Both JTAG-DP and SW-DP enabled, reset state.
SWJ_CFG_NO_NJTRST	Both JTAG-DP and SW-DP enabled, but NJTRST disabled and pin usable as GPIO.
SWJ_CFG_NO_JTAG_DP	Only SW-DP enabled, JTAG pins usable as GPIOS.
SWJ_CFG_DISABLED	Neither JTAG-DP nor SW-DP enabled, JTAG and SWD pins usable as GPIOS.

Definition at line 116 of file periph_cpu.h.

Function Documentation

afio_mapr_read()

static uint32_t afio_mapr_read ( void  )

inlinestatic

Read the current value of the AFIO->MAPR register reproducibly.

This will explicitly clear the write-only SWJ_CFG field [26:24], as the values read back are undefined.

Definition at line 154 of file periph_cpu.h.

afio_mapr_write()

static void afio_mapr_write ( uint32_t  new_value )

inlinestatic

Write to the AFIO->MAPR register apply the SWJ configuration specified via CONFIG_AFIO_MAPR_SWJ_CFG.

Precondition

new_value has all bits in the range [26:24] cleared (the SWJ_CFG field).

Definition at line 166 of file periph_cpu.h.