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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2016 Inria
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20/* HSE available on this board */
21#ifndef CONFIG_BOARD_HAS_HSE
22#define CONFIG_BOARD_HAS_HSE 1
23#endif
24
25/* This board provides an LSE */
26#ifndef CONFIG_BOARD_HAS_LSE
27#define CONFIG_BOARD_HAS_LSE 1
28#endif
29
30#include "periph_cpu.h"
31#include "clk_conf.h"
32#include "cfg_i2c1_pb8_pb9.h"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
42static const timer_conf_t timer_config[] = {
43 {
44 .dev = TIM1,
45 .max = 0x0000ffff,
46 .rcc_mask = RCC_APB2ENR_TIM1EN,
47 .bus = APB2,
48 .irqn = TIM1_CC_IRQn
49 }
50};
51
52#define TIMER_0_ISR isr_tim1_cc
53
54#define TIMER_NUMOF ARRAY_SIZE(timer_config)
56
61static const uart_conf_t uart_config[] = {
62 {
63 .dev = USART2,
64 .rcc_mask = RCC_APB1ENR_USART2EN,
65 .rx_pin = GPIO_PIN(PORT_A, 3),
66 .tx_pin = GPIO_PIN(PORT_A, 2),
67 .rx_af = GPIO_AF1,
68 .tx_af = GPIO_AF1,
69 .bus = APB1,
70 .irqn = USART2_IRQn
71 },
72 {
73 .dev = USART1,
74 .rcc_mask = RCC_APB2ENR_USART1EN,
75 .rx_pin = GPIO_PIN(PORT_A, 10),
76 .tx_pin = GPIO_PIN(PORT_A, 9),
77 .rx_af = GPIO_AF1,
78 .tx_af = GPIO_AF1,
79 .bus = APB2,
80 .irqn = USART1_IRQn
81 },
82 {
83 .dev = USART3,
84 .rcc_mask = RCC_APB1ENR_USART3EN,
85 .rx_pin = GPIO_PIN(PORT_C, 11),
86 .tx_pin = GPIO_PIN(PORT_C, 10),
87 .rx_af = GPIO_AF1,
88 .tx_af = GPIO_AF1,
89 .bus = APB1,
90 .irqn = USART3_4_IRQn
91 }
92};
93
94#define UART_0_ISR (isr_usart2)
95#define UART_1_ISR (isr_usart1)
96#define UART_2_ISR (isr_usart3_8)
97
98#define UART_NUMOF ARRAY_SIZE(uart_config)
100
105static const dma_conf_t dma_config[] = {
106 { .stream = 1 },
107 { .stream = 2 },
108};
109
110#define DMA_SHARED_ISR_0 isr_dma1_ch2_3_dma2_ch1_2
111#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
112
113#define DMA_NUMOF ARRAY_SIZE(dma_config)
115
120static const pwm_conf_t pwm_config[] = {
121 {
122 .dev = TIM3,
123 .rcc_mask = RCC_APB1ENR_TIM3EN,
124 .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
125 { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
126 { .pin = GPIO_UNDEF, .cc_chan = 0 },
127 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
128 .af = GPIO_AF1,
129 .bus = APB1
130 },
131 {
132 .dev = TIM15,
133 .rcc_mask = RCC_APB2ENR_TIM15EN,
134 .chan = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
135 { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
136 { .pin = GPIO_UNDEF, .cc_chan = 0 },
137 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
138 .af = GPIO_AF1,
139 .bus = APB2
140 }
141};
142
143#define PWM_NUMOF ARRAY_SIZE(pwm_config)
145
150static const adc_conf_t adc_config[] = {
151 { GPIO_PIN(PORT_A, 0), 0 },
152 { GPIO_PIN(PORT_A, 1), 1 },
153 { GPIO_PIN(PORT_A, 4), 4 },
154 { GPIO_PIN(PORT_B, 0), 8 },
155 { GPIO_PIN(PORT_C, 1), 11 },
156 { GPIO_PIN(PORT_C, 0), 10 }
157};
158
159#define ADC_NUMOF ARRAY_SIZE(adc_config)
161
173static const spi_conf_t spi_config[] = {
174 {
175 .dev = SPI1,
176 .mosi_pin = GPIO_PIN(PORT_A, 7),
177 .miso_pin = GPIO_PIN(PORT_A, 6),
178 .sclk_pin = GPIO_PIN(PORT_A, 5),
179 .cs_pin = GPIO_UNDEF,
180 .mosi_af = GPIO_AF0,
181 .miso_af = GPIO_AF0,
182 .sclk_af = GPIO_AF0,
183 .cs_af = GPIO_AF0,
184 .rccmask = RCC_APB2ENR_SPI1EN,
185 .apbbus = APB2,
186#ifdef MODULE_PERIPH_DMA
187 .tx_dma = 1,
188 .tx_dma_chan = 0,
189 .rx_dma = 0,
190 .rx_dma_chan = 0,
191#endif
192 }
193};
194
195#define SPI_NUMOF ARRAY_SIZE(spi_config)
197
198#ifdef __cplusplus
199}
200#endif
201
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF0
use alternate function 0
Definition cpu_gpio.h:101
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
DMA configuration.
Definition cpu_dma.h:31
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
Timer device configuration.
Definition periph_cpu.h:263
UART device configuration.
Definition periph_cpu.h:217