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periph_conf.h
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1/*
2 * Copyright (C) 2016 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32#include "periph_cpu.h"
33#include "clk_conf.h"
34#include "cfg_i2c1_pb8_pb9.h"
35#include "cfg_timer_tim5.h"
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
45static const dma_conf_t dma_config[] = {
46 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
47 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
48 { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */
49 { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */
50 { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */
51 { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */
52};
53
54#define DMA_0_ISR isr_dma2_stream3
55#define DMA_1_ISR isr_dma2_stream2
56#define DMA_2_ISR isr_dma1_stream4
57#define DMA_3_ISR isr_dma1_stream3
58#define DMA_4_ISR isr_dma1_stream5
59#define DMA_5_ISR isr_dma1_stream0
60
61#define DMA_NUMOF ARRAY_SIZE(dma_config)
68static const uart_conf_t uart_config[] = {
69 {
70 .dev = USART2,
71 .rcc_mask = RCC_APB1ENR_USART2EN,
72 .rx_pin = GPIO_PIN(PORT_A, 3),
73 .tx_pin = GPIO_PIN(PORT_A, 2),
74 .rx_af = GPIO_AF7,
75 .tx_af = GPIO_AF7,
76 .bus = APB1,
77 .irqn = USART2_IRQn,
78#ifdef MODULE_PERIPH_DMA
79 .dma = DMA_STREAM_UNDEF,
80 .dma_chan = UINT8_MAX,
81#endif
82 },
83 {
84 .dev = USART1,
85 .rcc_mask = RCC_APB2ENR_USART1EN,
86 .rx_pin = GPIO_PIN(PORT_A, 10),
87 .tx_pin = GPIO_PIN(PORT_A, 9),
88 .rx_af = GPIO_AF7,
89 .tx_af = GPIO_AF7,
90 .bus = APB2,
91 .irqn = USART1_IRQn,
92#ifdef MODULE_PERIPH_DMA
93 .dma = DMA_STREAM_UNDEF,
94 .dma_chan = UINT8_MAX,
95#endif
96 },
97 {
98 .dev = USART3,
99 .rcc_mask = RCC_APB1ENR_USART3EN,
100 .rx_pin = GPIO_PIN(PORT_C, 11),
101 .tx_pin = GPIO_PIN(PORT_C, 10),
102 .rx_af = GPIO_AF7,
103 .tx_af = GPIO_AF7,
104 .bus = APB1,
105 .irqn = USART3_IRQn,
106#ifdef MODULE_PERIPH_DMA
107 .dma = DMA_STREAM_UNDEF,
108 .dma_chan = UINT8_MAX,
109#endif
110 },
111};
112
113#define UART_0_ISR (isr_usart2)
114#define UART_1_ISR (isr_usart1)
115#define UART_2_ISR (isr_usart3)
116
117#define UART_NUMOF ARRAY_SIZE(uart_config)
124static const pwm_conf_t pwm_config[] = {
125 {
126 .dev = TIM2,
127 .rcc_mask = RCC_APB1ENR_TIM2EN,
128 .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
129 { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
130 { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
131 { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
132 .af = GPIO_AF1,
133 .bus = APB1
134 },
135 {
136 .dev = TIM8,
137 .rcc_mask = RCC_APB2ENR_TIM8EN,
138 .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
139 { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
140 { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
141 { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
142 .af = GPIO_AF3,
143 .bus = APB2
144 },
145};
146
147#define PWM_NUMOF ARRAY_SIZE(pwm_config)
154static const qdec_conf_t qdec_config[] = {
155 {
156 .dev = TIM3,
157 .max = 0xffffffff,
158 .rcc_mask = RCC_APB1ENR_TIM3EN,
159 .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
160 { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
161 .af = GPIO_AF2,
162 .bus = APB1,
163 .irqn = TIM3_IRQn
164 },
165 {
166 .dev = TIM4,
167 .max = 0xffffffff,
168 .rcc_mask = RCC_APB1ENR_TIM4EN,
169 .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
170 { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
171 .af = GPIO_AF2,
172 .bus = APB1,
173 .irqn = TIM4_IRQn
174 },
175};
176
177#define QDEC_0_ISR isr_tim3
178#define QDEC_1_ISR isr_tim4
179
180#define QDEC_NUMOF ARRAY_SIZE(qdec_config)
187static const spi_conf_t spi_config[] = {
188 {
189 .dev = SPI1,
190 .mosi_pin = GPIO_PIN(PORT_A, 7),
191 .miso_pin = GPIO_PIN(PORT_A, 6),
192 .sclk_pin = GPIO_PIN(PORT_A, 5),
193 .cs_pin = GPIO_PIN(PORT_A, 4),
194 .mosi_af = GPIO_AF5,
195 .miso_af = GPIO_AF5,
196 .sclk_af = GPIO_AF5,
197 .cs_af = GPIO_AF5,
198 .rccmask = RCC_APB2ENR_SPI1EN,
199 .apbbus = APB2,
200#ifdef MODULE_PERIPH_DMA
201 .tx_dma = 0,
202 .tx_dma_chan = 3,
203 .rx_dma = 1,
204 .rx_dma_chan = 3,
205#endif
206 },
207 {
208 .dev = SPI2,
209 .mosi_pin = GPIO_PIN(PORT_B, 15),
210 .miso_pin = GPIO_PIN(PORT_B, 14),
211 .sclk_pin = GPIO_PIN(PORT_B, 13),
212 .cs_pin = GPIO_PIN(PORT_B, 12),
213 .mosi_af = GPIO_AF5,
214 .miso_af = GPIO_AF5,
215 .sclk_af = GPIO_AF5,
216 .cs_af = GPIO_AF5,
217 .rccmask = RCC_APB1ENR_SPI2EN,
218 .apbbus = APB1,
219#ifdef MODULE_PERIPH_DMA
220 .tx_dma = 2,
221 .tx_dma_chan = 0,
222 .rx_dma = 3,
223 .rx_dma_chan = 0,
224#endif
225 },
226 {
227 .dev = SPI3,
228 .mosi_pin = GPIO_PIN(PORT_C, 12),
229 .miso_pin = GPIO_PIN(PORT_C, 11),
230 .sclk_pin = GPIO_PIN(PORT_C, 10),
231 .cs_pin = GPIO_UNDEF,
232 .mosi_af = GPIO_AF6,
233 .miso_af = GPIO_AF6,
234 .sclk_af = GPIO_AF6,
235 .cs_af = GPIO_AF6,
236 .rccmask = RCC_APB1ENR_SPI3EN,
237 .apbbus = APB1,
238#ifdef MODULE_PERIPH_DMA
239 .tx_dma = 4,
240 .tx_dma_chan = 0,
241 .rx_dma = 5,
242 .rx_dma_chan = 0,
243#endif
244 }
245};
246
247#define SPI_NUMOF ARRAY_SIZE(spi_config)
260static const adc_conf_t adc_config[] = {
261 {GPIO_PIN(PORT_A, 0), 0, 0},
262 {GPIO_PIN(PORT_A, 1), 0, 1},
263 {GPIO_PIN(PORT_A, 4), 0, 4},
264 {GPIO_PIN(PORT_B, 0), 0, 8},
265 {GPIO_PIN(PORT_C, 1), 0, 11},
266 {GPIO_PIN(PORT_C, 0), 0, 10},
267 {GPIO_UNDEF, 0, 18}, /* VBAT */
268};
269
270#define VBAT_ADC ADC_LINE(6)
271#define ADC_NUMOF ARRAY_SIZE(adc_config)
274#ifdef __cplusplus
275}
276#endif
277
278#endif /* PERIPH_CONF_H */
PORT_B
@ PORT_B
port B
Definition periph_cpu.h:48
PORT_C
@ PORT_C
port C
Definition periph_cpu.h:49
PORT_A
@ PORT_A
port A
Definition periph_cpu.h:47
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition periph_cpu_common.h:54
cfg_i2c1_pb8_pb9.h
Common configuration for STM32 I2C.
cfg_timer_tim5.h
Common configuration for STM32 Timer peripheral based on TIM5.
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:104
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition cpu_gpio.h:108
GPIO_AF3
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:105
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
APB1
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
APB2
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
adc_conf_t
ADC device configuration.
Definition periph_cpu.h:379
dma_conf_t
DMA configuration.
Definition cpu_dma.h:32
dma_conf_t::stream
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition cpu_dma.h:55
pwm_conf_t
PWM device configuration.
Definition periph_cpu_common.h:323
pwm_conf_t::dev
mini_timer_t * dev
Timer used.
Definition periph_cpu_common.h:324
qdec_conf_t
Quadrature decoder configuration struct.
Definition periph_cpu_common.h:368
qdec_conf_t::dev
TIM_TypeDef * dev
Timer used.
Definition cpu_qdec.h:50
spi_conf_t
SPI device configuration.
Definition periph_cpu.h:337
spi_conf_t::dev
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
uart_conf_t
UART device configuration.
Definition periph_cpu.h:218
uart_conf_t::dev
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219