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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* Add specific clock configuration (HSE, LSE) for this board here */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23#include "periph_cpu.h"
24#include "clk_conf.h"
25#include "cfg_rtt_default.h"
26#include "cfg_timer_tim2.h"
27#include "cfg_usb_otg_fs.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37static const uart_conf_t uart_config[] = {
38 {
39 .dev = USART2,
40 .rcc_mask = RCC_APB1ENR1_USART2EN,
41 .rx_pin = GPIO_PIN(PORT_D, 6),
42 .tx_pin = GPIO_PIN(PORT_A, 2),
43 .rx_af = GPIO_AF7,
44 .tx_af = GPIO_AF7,
45 .bus = APB1,
46 .irqn = USART2_IRQn,
47#ifdef MODULE_PERIPH_UART_HW_FC
48 .cts_pin = GPIO_UNDEF,
49 .rts_pin = GPIO_UNDEF,
50 .cts_af = GPIO_AF7,
51 .rts_af = GPIO_AF7,
52#endif
53 .type = STM32_USART,
54 .clk_src = 0, /* Use APB clock */
55 },
56 { /* Arduino pinout RX/TX pins on D0/D1 */
57 .dev = LPUART1,
58 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
59 .rx_pin = GPIO_PIN(PORT_G, 8),
60 .tx_pin = GPIO_PIN(PORT_G, 7),
61 .rx_af = GPIO_AF8,
62 .tx_af = GPIO_AF8,
63 .bus = APB12,
64 .irqn = LPUART1_IRQn,
65#ifdef MODULE_PERIPH_UART_HW_FC
66 .cts_pin = GPIO_UNDEF,
67 .rts_pin = GPIO_UNDEF,
68 .cts_af = GPIO_AF7,
69 .rts_af = GPIO_AF7,
70#endif
71 .type = STM32_LPUART,
72 .clk_src = 0,
73 },
74 { /* STMod+/PMOD connectors */
75 .dev = USART1,
76 .rcc_mask = RCC_APB2ENR_USART1EN,
77 .rx_pin = GPIO_PIN(PORT_G, 10),
78 .tx_pin = GPIO_PIN(PORT_B, 6),
79 .rx_af = GPIO_AF7,
80 .tx_af = GPIO_AF7,
81 .bus = APB2,
82 .irqn = USART1_IRQn,
83#ifdef MODULE_PERIPH_UART_HW_FC
84 .cts_pin = GPIO_PIN(PORT_G, 11),
85 .rts_pin = GPIO_PIN(PORT_G, 12),
86 .cts_af = GPIO_AF7,
87 .rts_af = GPIO_AF7,
88#endif
89 .type = STM32_USART,
90 .clk_src = 0, /* Use APB clock */
91 }
92};
93
94#define UART_0_ISR (isr_usart2)
95#define UART_1_ISR (isr_lpuart1)
96#define UART_2_ISR (isr_usart1)
97
98#define UART_NUMOF ARRAY_SIZE(uart_config)
100
105static const i2c_conf_t i2c_config[] = {
106 {
107 .dev = I2C1,
108 .speed = I2C_SPEED_NORMAL,
109 .scl_pin = GPIO_PIN(PORT_B, 8),
110 .sda_pin = GPIO_PIN(PORT_B, 7),
111 .scl_af = GPIO_AF4,
112 .sda_af = GPIO_AF4,
113 .bus = APB1,
114 .rcc_mask = RCC_APB1ENR1_I2C1EN,
115 .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
116 .irqn = I2C1_ER_IRQn
117 },
118};
119
120#define I2C_0_ISR isr_i2c1_er
121
122#define I2C_NUMOF ARRAY_SIZE(i2c_config)
124
129static const spi_conf_t spi_config[] = {
130 {
131 .dev = SPI1,
132 .mosi_pin = GPIO_PIN(PORT_B, 5),
133 .miso_pin = GPIO_PIN(PORT_B, 4),
134 .sclk_pin = GPIO_PIN(PORT_A, 5),
135 .cs_pin = SPI_CS_UNDEF,
136 .mosi_af = GPIO_AF5,
137 .miso_af = GPIO_AF5,
138 .sclk_af = GPIO_AF5,
139 .cs_af = GPIO_AF5,
140 .rccmask = RCC_APB2ENR_SPI1EN,
141 .apbbus = APB2
142 }
143};
144
145#define SPI_NUMOF ARRAY_SIZE(spi_config)
147
148#ifdef __cplusplus
149}
150#endif
151
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
Common configuration for STM32 Timer peripheral based on TIM2.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:38
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217