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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_timer_tim5.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
41static const dma_conf_t dma_config[] = {
42 { .stream = 14 }, /* DMA2 Stream 6 - SPI5_TX */
43 { .stream = 13 }, /* DMA2 Stream 5 - SPI5_RX */
44};
45
46#define DMA_0_ISR isr_dma2_stream6
47#define DMA_1_ISR isr_dma2_stream5
48
49#define DMA_NUMOF ARRAY_SIZE(dma_config)
51
56static const uart_conf_t uart_config[] = {
57 {
58 .dev = USART1,
59 .rcc_mask = RCC_APB2ENR_USART1EN,
60 .rx_pin = GPIO_PIN(PORT_A, 10),
61 .tx_pin = GPIO_PIN(PORT_A, 9),
62 .rx_af = GPIO_AF7,
63 .tx_af = GPIO_AF7,
64 .bus = APB2,
65 .irqn = USART1_IRQn,
66#ifdef MODULE_PERIPH_DMA
67 .dma = DMA_STREAM_UNDEF,
68 .dma_chan = UINT8_MAX,
69#endif
70 }
71};
72
73#define UART_0_ISR (isr_usart1)
74
75#define UART_NUMOF ARRAY_SIZE(uart_config)
77
82static const spi_conf_t spi_config[] = {
83 {
84 .dev = SPI5,
85 .mosi_pin = GPIO_PIN(PORT_F, 9),
86 .miso_pin = GPIO_PIN(PORT_F, 8),
87 .sclk_pin = GPIO_PIN(PORT_F, 7),
88 .cs_pin = GPIO_UNDEF,
89 .mosi_af = GPIO_AF5,
90 .miso_af = GPIO_AF5,
91 .sclk_af = GPIO_AF5,
92 .cs_af = GPIO_AF5,
93 .rccmask = RCC_APB2ENR_SPI5EN,
94 .apbbus = APB2,
95#ifdef MODULE_PERIPH_DMA
96 .tx_dma = 0,
97 .tx_dma_chan = 7,
98 .rx_dma = 1,
99 .rx_dma_chan = 7,
100#endif
101 }
102};
103
104#define SPI_NUMOF ARRAY_SIZE(spi_config)
106
111static const i2c_conf_t i2c_config[] = {
112 {
113 .dev = I2C3,
114 .speed = I2C_SPEED_NORMAL,
115 .scl_pin = GPIO_PIN(PORT_A, 8),
116 .sda_pin = GPIO_PIN(PORT_C, 9),
117 .scl_af = GPIO_AF4,
118 .sda_af = GPIO_AF4,
119 .bus = APB1,
120 .rcc_mask = RCC_APB1ENR_I2C3EN,
121 .clk = CLOCK_APB1,
122 .irqn = I2C3_EV_IRQn,
123 }
124};
125
126#define I2C_0_ISR isr_i2c3_ev
127
128#define I2C_NUMOF ARRAY_SIZE(i2c_config)
130
138static const fmc_conf_t fmc_config = {
139 .bus = AHB3,
140 .rcc_mask = RCC_AHB3ENR_FMCEN,
141#if MODULE_PERIPH_FMC_SDRAM
142 .ba0_pin = { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* FMC_BA0 signal */
143 .ba1_pin = { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* FMC_BA1 signal */
144 .sdclk_pin = { .pin = GPIO_PIN(PORT_G, 8), .af = GPIO_AF12, }, /* FMC_SDCLK signal */
145 .sdnwe_pin = { .pin = GPIO_PIN(PORT_C, 0), .af = GPIO_AF12, }, /* FMC_SDNWE signal */
146 .sdnras_pin = { .pin = GPIO_PIN(PORT_F, 11), .af = GPIO_AF12, }, /* FMC_SDNRAS signal */
147 .sdncas_pin = { .pin = GPIO_PIN(PORT_G, 15), .af = GPIO_AF12, }, /* FMC_SDNCAS signal */
148 .sdcke1_pin = { .pin = GPIO_PIN(PORT_B, 5), .af = GPIO_AF12, }, /* FMC_SDCKE1 signal */
149 .sdne1_pin = { .pin = GPIO_PIN(PORT_B, 6), .af = GPIO_AF12, }, /* FMC_SDNE1 signal */
150 .addr = {
151 { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* FMC_A0 signal */
152 { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* FMC_A1 signal */
153 { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* FMC_A2 signal */
154 { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* FMC_A3 signal */
155 { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* FMC_A4 signal */
156 { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* FMC_A5 signal */
157 { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* FMC_A6 signal */
158 { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* FMC_A7 signal */
159 { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* FMC_A8 signal */
160 { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* FMC_A9 signal */
161 { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* FMC_A10 signal */
162 { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* FMC_A11 signal */
163 },
164#endif
165 .data = {
166 { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* FMC_D0 signal */
167 { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* FMC_D1 signal */
168 { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* FMC_D2 signal */
169 { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* FMC_D3 signal */
170 { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* FMC_D4 signal */
171 { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* FMC_D5 signal */
172 { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* FMC_D6 signal */
173 { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* FMC_D7 signal */
174#if MODULE_PERIPH_FMC_16BIT
175 { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* FMC_D8 signal */
176 { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* FMC_D9 signal */
177 { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* FMC_D10 signal */
178 { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* FMC_D11 signal */
179 { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* FMC_D12 signal */
180 { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* FMC_D13 signal */
181 { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* FMC_D14 signal */
182 { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* FMC_D15 signal */
183#endif
184 },
185 .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* FMC_NBL0 signal (LB) */
186 .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* FMC_NBL1 signal (UB) */
187};
188
197 /* bank 6 is used for SDRAM */
198 {
199 .bank = FMC_BANK_6,
200 .mem_type = FMC_SDRAM,
201 .data_width = FMC_BUS_WIDTH_16BIT,
202 .address = 0xd0000000, /* Bank 6 is mapped to 0xd0000000 */
203 .size = MiB(8), /* Size in Mbyte, 4M x 16 bit */
204 .sdram = {
205 .clk_period = 2, /* SDCLK = 2 x HCLK */
206 .row_bits = 12, /* A11..A0 used for row address */
207 .col_bits = 8, /* A8..A0 used for column address */
208 .cas_latency = 3, /* CAS latency is 3 clock cycles */
209 .read_delay = 0, /* No read delay after CAS */
210 .burst_read = false, /* Burst read mode disabled */
211 .burst_write = false, /* Burst write mode disabled */
212 .burst_len = FMC_BURST_LENGTH_1, /* Burst length is 1 if enabled */
213 .burst_interleaved = false, /* Burst mode interleaved */
214 .write_protect = false, /* No write protection */
215 .four_banks = true, /* SDRAM has four internal banks */
216 .timing = { /* SDRAM Timing parameters */
217 .row_to_col_delay = 2, /* Row to column delay (2 clock cycles) */
218 .row_precharge = 2, /* Row precharge delay (2 clock cycles) */
219 .recovery_delay = 2, /* Recovery delay is (2 clock cycles) */
220 .row_cylce = 7, /* Row cycle delay is (7 clock cycles) */
221 .self_refresh = 4, /* Self refresh time is (4 clock cycles) */
222 .exit_self_refresh = 7, /* Exit self-refresh delay (7 clock cycles) */
223 .load_mode_register = 2, /* Load Mode Register to Activate delay */
224 .refresh_period = 64, /* Refresh period in ms */
225 },
226 },
227 },
228};
229
233#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
235
236#ifdef __cplusplus
237}
238#endif
239
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_F
port F
Definition periph_cpu.h:51
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:277
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
static const fmc_conf_t fmc_config
FMC controller configuration.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG HS peripheral with on-chip FS PHY.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
@ GPIO_AF12
use alternate function 12
Definition cpu_gpio.h:114
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
@ FMC_SDRAM
SDRAM Controller used.
Definition cpu_fmc.h:344
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition cpu_fmc.h:352
DMA configuration.
Definition cpu_dma.h:31
Bank configuration structure.
Definition cpu_fmc.h:359
FMC peripheral configuration.
Definition cpu_fmc.h:277
I2C configuration structure.
Definition periph_cpu.h:298
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217
#define MiB(x)
A macro to return the bytes in x MiB.
Definition units.h:33