Loading...
Searching...
No Matches
periph_conf.h
Go to the documentation of this file.
1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
31#include "cfg_timer_tim5.h"
32#include "cfg_usb_otg_fs.h"
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
42static const dma_conf_t dma_config[] = {
43 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
44 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
45};
46
47#define DMA_0_ISR isr_dma2_stream3
48#define DMA_1_ISR isr_dma2_stream2
49
50#define DMA_NUMOF ARRAY_SIZE(dma_config)
52
57static const uart_conf_t uart_config[] = {
58 {
59 .dev = USART3,
60 .rcc_mask = RCC_APB1ENR_USART3EN,
61 .rx_pin = GPIO_PIN(PORT_D, 9),
62 .tx_pin = GPIO_PIN(PORT_D, 8),
63 .rx_af = GPIO_AF7,
64 .tx_af = GPIO_AF7,
65 .bus = APB1,
66 .irqn = USART3_IRQn,
67#ifdef MODULE_PERIPH_DMA
68 .dma = DMA_STREAM_UNDEF,
69 .dma_chan = UINT8_MAX,
70#endif
71 },
72 {
73 .dev = USART6,
74 .rcc_mask = RCC_APB2ENR_USART6EN,
75 .rx_pin = GPIO_PIN(PORT_G, 9),
76 .tx_pin = GPIO_PIN(PORT_G, 14),
77 .rx_af = GPIO_AF8,
78 .tx_af = GPIO_AF8,
79 .bus = APB2,
80 .irqn = USART6_IRQn,
81#ifdef MODULE_PERIPH_DMA
82 .dma = DMA_STREAM_UNDEF,
83 .dma_chan = UINT8_MAX,
84#endif
85 },
86 {
87 .dev = USART2,
88 .rcc_mask = RCC_APB1ENR_USART2EN,
89 .rx_pin = GPIO_PIN(PORT_D, 6),
90 .tx_pin = GPIO_PIN(PORT_D, 5),
91 .rx_af = GPIO_AF7,
92 .tx_af = GPIO_AF7,
93 .bus = APB1,
94 .irqn = USART2_IRQn,
95#ifdef MODULE_PERIPH_DMA
96 .dma = DMA_STREAM_UNDEF,
97 .dma_chan = UINT8_MAX,
98#endif
99 },
100};
101
102#define UART_0_ISR (isr_usart3)
103#define UART_1_ISR (isr_usart6)
104#define UART_2_ISR (isr_usart2)
105
106#define UART_NUMOF ARRAY_SIZE(uart_config)
108
113static const pwm_conf_t pwm_config[] = {
114 {
115 .dev = TIM1,
116 .rcc_mask = RCC_APB2ENR_TIM1EN,
117 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
118 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
119 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
120 { .pin = GPIO_UNDEF, .cc_chan = 0} },
121 .af = GPIO_AF1,
122 .bus = APB2
123 },
124 {
125 .dev = TIM4,
126 .rcc_mask = RCC_APB1ENR_TIM4EN,
127 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
128 { .pin = GPIO_UNDEF, .cc_chan = 0},
129 { .pin = GPIO_UNDEF, .cc_chan = 0},
130 { .pin = GPIO_UNDEF, .cc_chan = 0} },
131 .af = GPIO_AF2,
132 .bus = APB1
133 },
134};
135
136#define PWM_NUMOF ARRAY_SIZE(pwm_config)
138
143static const spi_conf_t spi_config[] = {
144 {
145 .dev = SPI1,
146 .mosi_pin = GPIO_PIN(PORT_A, 7),
147 .miso_pin = GPIO_PIN(PORT_A, 6),
148 .sclk_pin = GPIO_PIN(PORT_A, 5),
149 .cs_pin = SPI_CS_UNDEF,
150 .mosi_af = GPIO_AF5,
151 .miso_af = GPIO_AF5,
152 .sclk_af = GPIO_AF5,
153 .cs_af = GPIO_AF5,
154 .rccmask = RCC_APB2ENR_SPI1EN,
155 .apbbus = APB2,
156#ifdef MODULE_PERIPH_DMA
157 .tx_dma = 0,
158 .tx_dma_chan = 3,
159 .rx_dma = 1,
160 .rx_dma_chan = 3,
161#endif
162 },
163};
164
165#define SPI_NUMOF ARRAY_SIZE(spi_config)
167
189static const adc_conf_t adc_config[] = {
190 { .pin = GPIO_PIN(PORT_A, 0), .dev = 2, .chan = 3 }, /* ADC123_IN3 */
191 { .pin = GPIO_PIN(PORT_A, 1), .dev = 2, .chan = 10 }, /* ADC123_IN10 */
192 { .pin = GPIO_PIN(PORT_A, 4), .dev = 2, .chan = 13 }, /* ADC123_IN13 */
193 { .pin = GPIO_PIN(PORT_B, 0), .dev = 2, .chan = 9 }, /* ADC123_IN9 */
194 { .pin = GPIO_PIN(PORT_C, 1), .dev = 2, .chan = 15 }, /* ADC3_IN15 */
195 { .pin = GPIO_PIN(PORT_C, 0), .dev = 2, .chan = 8 }, /* ADC3_IN8 */
196 { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* VBAT */
197};
198
202#define ADC_NUMOF ARRAY_SIZE(adc_config)
203
204#define VBAT_ADC ADC_LINE(6)
205
207
208#ifdef __cplusplus
209}
210#endif
211
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
ADC device configuration.
Definition periph_cpu.h:377
DMA configuration.
Definition cpu_dma.h:31
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217