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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2024 Prime Controls, Inc.(R)
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#ifndef CONFIG_BOARD_HAS_LSE
19# define CONFIG_BOARD_HAS_LSE 1
20#endif
21
22#ifndef CONFIG_BOARD_HAS_HSE
23# define CONFIG_BOARD_HAS_HSE 1
24#endif
25
26#include "periph_cpu.h"
27#include "clk_conf.h"
28#include "cfg_i2c1_pb8_pb9.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
40static const dma_conf_t dma_config[] = {
41 { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
42 { .stream = 14 }, /* DMA2 Stream 14 - USART6_TX */
43 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
44};
45
46#define DMA_0_ISR isr_dma1_stream4
47#define DMA_1_ISR isr_dma2_stream6
48#define DMA_2_ISR isr_dma1_stream6
49
50#define DMA_NUMOF ARRAY_SIZE(dma_config)
52
58static const uart_conf_t uart_config[] = {
59 {
60 .dev = USART3,
61 .rcc_mask = RCC_APB1LENR_USART3EN,
62 .rx_pin = GPIO_PIN(PORT_D, 9),
63 .tx_pin = GPIO_PIN(PORT_D, 8),
64 .rx_af = GPIO_AF7,
65 .tx_af = GPIO_AF7,
66 .bus = APB1,
67 .irqn = USART3_IRQn,
68 .type = STM32_USART,
69 .clk_src = 0, /* Use APB clock */
70#ifdef MODULE_PERIPH_DMA
71 .dma = 0,
72 .dma_chan = 46 /* DMAMUX_REQ_USART3_TX */
73#endif
74 },
75 {
76 .dev = USART6,
77 .rcc_mask = RCC_APB2ENR_USART6EN,
78 .rx_pin = GPIO_PIN(PORT_G, 9),
79 .tx_pin = GPIO_PIN(PORT_G, 14),
80 .rx_af = GPIO_AF7,
81 .tx_af = GPIO_AF7,
82 .bus = APB2,
83 .irqn = USART6_IRQn,
84 .type = STM32_USART,
85 .clk_src = 0, /* Use APB clock */
86#ifdef MODULE_PERIPH_DMA
87 .dma = 1,
88 .dma_chan = 72 /* DMAMUX_REQ_USART6_TX */
89#endif
90 },
91 {
92 .dev = USART2,
93 .rcc_mask = RCC_APB1LENR_USART2EN,
94 .rx_pin = GPIO_PIN(PORT_D, 6),
95 .tx_pin = GPIO_PIN(PORT_D, 5),
96 .rx_af = GPIO_AF7,
97 .tx_af = GPIO_AF7,
98 .bus = APB1,
99 .irqn = USART2_IRQn,
100 .type = STM32_USART,
101 .clk_src = 0, /* Use APB clock */
102#ifdef MODULE_PERIPH_DMA
103 .dma = 2,
104 .dma_chan = 44 /* DMAMUX_REQ_USART2_TX */
105#endif
106 },
107 {
108 .dev = LPUART1,
109 .rcc_mask = RCC_APB4ENR_LPUART1EN,
110 .rx_pin = GPIO_PIN(PORT_B, 7), /* connected to D0 */
111 .tx_pin = GPIO_PIN(PORT_B, 6), /* connected to D1 */
112 .rx_af = GPIO_AF8,
113 .tx_af = GPIO_AF8,
114 .bus = APB4,
115 .irqn = LPUART1_IRQn,
116 .type = STM32_LPUART,
117 .clk_src = 0, /* Use APB clock */
118 /* the LPUART uses the BDMA controller rather than the normal DMA controller */
119 },
120};
121
122#define UART_0_ISR (isr_usart3)
123#define UART_1_ISR (isr_usart6)
124#define UART_2_ISR (isr_usart2)
125#define UART_3_ISR (isr_lpuart1)
126#define UART_NUMOF ARRAY_SIZE(uart_config)
128
133static const spi_conf_t spi_config[] = {
134 {
135 .dev = SPI1,
136 .mosi_pin = GPIO_PIN(PORT_B, 5),
137 .miso_pin = GPIO_PIN(PORT_A, 6),
138 .sclk_pin = GPIO_PIN(PORT_A, 5),
139 .cs_pin = GPIO_PIN(PORT_A, 4), /* For HW NSS */
140 .mosi_af = GPIO_AF5,
141 .miso_af = GPIO_AF5,
142 .sclk_af = GPIO_AF5,
143 .cs_af = GPIO_AF5,
144 .rccmask = RCC_APB2ENR_SPI1EN,
145 .apbbus = APB2
146 },
147 {
148 .dev = SPI4,
149 .mosi_pin = GPIO_PIN(PORT_E, 6),
150 .miso_pin = GPIO_PIN(PORT_E, 5),
151 .sclk_pin = GPIO_PIN(PORT_E, 2),
152 .cs_pin = GPIO_PIN(PORT_E, 4), /* For HW NSS */
153 .mosi_af = GPIO_AF5,
154 .miso_af = GPIO_AF5,
155 .sclk_af = GPIO_AF5,
156 .cs_af = GPIO_AF5,
157 .rccmask = RCC_APB2ENR_SPI4EN,
158 .apbbus = APB2
159 }
160};
161#define SPI_NUMOF ARRAY_SIZE(spi_config)
163
169static const adc_conf_t adc_config[] = {
170 {GPIO_PIN(PORT_A, 3), 0, 15},
171 {GPIO_PIN(PORT_C, 0), 1, 10},
172 {GPIO_PIN(PORT_C, 3), 0, 13},
173 {GPIO_PIN(PORT_B, 1), 1, 5},
174 {GPIO_PIN(PORT_C, 2), 0, 12},
175 {GPIO_PIN(PORT_F, 10), 2, 6},
176 {GPIO_UNDEF, 2, 17}, /* VBAT */
177};
178
182#define VBAT_ADC ADC_LINE(6)
183#define ADC_NUMOF ARRAY_SIZE(adc_config)
185
190static const pwm_conf_t pwm_config[] = {
191 {
192 .dev = TIM1,
193 .rcc_mask = RCC_APB2ENR_TIM1EN,
194 .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0},
195 { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1},
196 { .pin = GPIO_PIN(PORT_E, 13), .cc_chan = 2},
197 { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3} },
198 .af = GPIO_AF1,
199 .bus = APB2
200 },
201 {
202 .dev = TIM4,
203 .rcc_mask = RCC_APB1LENR_TIM4EN,
204 .chan = { { .pin = GPIO_PIN(PORT_D, 12), .cc_chan = 0},
205 { .pin = GPIO_PIN(PORT_D, 13), .cc_chan = 1},
206 { .pin = GPIO_PIN(PORT_D, 14), .cc_chan = 2},
207 { .pin = GPIO_PIN(PORT_D, 15), .cc_chan = 3} },
208 .af = GPIO_AF2,
209 .bus = APB1
210 },
211};
212#define PWM_NUMOF ARRAY_SIZE(pwm_config)
214
215#ifdef __cplusplus
216}
217#endif
218
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_F
port F
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5 and TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:99
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:100
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:103
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:107
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:105
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:35
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:34
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
ADC device configuration.
Definition periph_cpu.h:375
DMA configuration.
Definition cpu_dma.h:28
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214