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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2024 Prime Controls, Inc.(R)
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18#ifndef CONFIG_BOARD_HAS_LSE
19# define CONFIG_BOARD_HAS_LSE 1
20#endif
21
22#ifndef CONFIG_BOARD_HAS_HSE
23# define CONFIG_BOARD_HAS_HSE 1
24#endif
25
26#include "periph_cpu.h"
27#include "clk_conf.h"
28#include "cfg_i2c1_pb8_pb9.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
40static const dma_conf_t dma_config[] = {
41 { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */
42 { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */
43 { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */
44};
45
46#define DMA_0_ISR isr_dma1_stream4
47#define DMA_1_ISR isr_dma2_stream6
48#define DMA_2_ISR isr_dma1_stream6
49
50#define DMA_NUMOF ARRAY_SIZE(dma_config)
52
58static const uart_conf_t uart_config[] = {
59 {
60 .dev = USART3,
61 .rcc_mask = RCC_APB1LENR_USART3EN,
62 .rx_pin = GPIO_PIN(PORT_D, 9),
63 .tx_pin = GPIO_PIN(PORT_D, 8),
64 .rx_af = GPIO_AF7,
65 .tx_af = GPIO_AF7,
66 .bus = APB1,
67 .irqn = USART3_IRQn,
68#ifdef MODULE_PERIPH_DMA
69 .dma = 0,
70 .dma_chan = 46 /* DMAMUX_REQ_USART3_TX */
71#endif
72 },
73 {
74 .dev = USART6,
75 .rcc_mask = RCC_APB2ENR_USART6EN,
76 .rx_pin = GPIO_PIN(PORT_G, 9),
77 .tx_pin = GPIO_PIN(PORT_G, 14),
78 .rx_af = GPIO_AF7,
79 .tx_af = GPIO_AF7,
80 .bus = APB2,
81 .irqn = USART6_IRQn,
82#ifdef MODULE_PERIPH_DMA
83 .dma = 1,
84 .dma_chan = 72 /* DMAMUX_REQ_USART6_TX */
85#endif
86 },
87 {
88 .dev = USART2,
89 .rcc_mask = RCC_APB1LENR_USART2EN,
90 .rx_pin = GPIO_PIN(PORT_D, 6),
91 .tx_pin = GPIO_PIN(PORT_D, 5),
92 .rx_af = GPIO_AF7,
93 .tx_af = GPIO_AF7,
94 .bus = APB1,
95 .irqn = USART2_IRQn,
96#ifdef MODULE_PERIPH_DMA
97 .dma = 2,
98 .dma_chan = 44 /* DMAMUX_REQ_USART2_TX */
99#endif
100 }
101};
102
103#define UART_0_ISR (isr_usart3)
104#define UART_1_ISR (isr_usart6)
105#define UART_2_ISR (isr_usart2)
106#define UART_NUMOF ARRAY_SIZE(uart_config)
108
113static const spi_conf_t spi_config[] = {
114 {
115 .dev = SPI1,
116 .mosi_pin = GPIO_PIN(PORT_B, 5),
117 .miso_pin = GPIO_PIN(PORT_A, 6),
118 .sclk_pin = GPIO_PIN(PORT_A, 5),
119 .cs_pin = GPIO_PIN(PORT_A, 4), /* For HW NSS */
120 .mosi_af = GPIO_AF5,
121 .miso_af = GPIO_AF5,
122 .sclk_af = GPIO_AF5,
123 .cs_af = GPIO_AF5,
124 .rccmask = RCC_APB2ENR_SPI1EN,
125 .apbbus = APB2
126 },
127 {
128 .dev = SPI4,
129 .mosi_pin = GPIO_PIN(PORT_E, 6),
130 .miso_pin = GPIO_PIN(PORT_E, 5),
131 .sclk_pin = GPIO_PIN(PORT_E, 2),
132 .cs_pin = GPIO_PIN(PORT_E, 4), /* For HW NSS */
133 .mosi_af = GPIO_AF5,
134 .miso_af = GPIO_AF5,
135 .sclk_af = GPIO_AF5,
136 .cs_af = GPIO_AF5,
137 .rccmask = RCC_APB2ENR_SPI4EN,
138 .apbbus = APB2
139 }
140};
141#define SPI_NUMOF ARRAY_SIZE(spi_config)
143
149static const adc_conf_t adc_config[] = {
150 {GPIO_PIN(PORT_A, 3), 0, 15},
151 {GPIO_PIN(PORT_C, 0), 1, 10},
152 {GPIO_PIN(PORT_C, 3), 0, 13},
153 {GPIO_PIN(PORT_B, 1), 1, 5},
154 {GPIO_PIN(PORT_C, 2), 0, 12},
155 {GPIO_PIN(PORT_F, 10), 2, 6},
156 {GPIO_UNDEF, 2, 17}, /* VBAT */
157};
158
162#define VBAT_ADC ADC_LINE(6)
163#define ADC_NUMOF ARRAY_SIZE(adc_config)
165
170static const pwm_conf_t pwm_config[] = {
171 {
172 .dev = TIM1,
173 .rcc_mask = RCC_APB2ENR_TIM1EN,
174 .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0},
175 { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1},
176 { .pin = GPIO_PIN(PORT_E, 13), .cc_chan = 2},
177 { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3} },
178 .af = GPIO_AF1,
179 .bus = APB2
180 },
181 {
182 .dev = TIM4,
183 .rcc_mask = RCC_APB1LENR_TIM4EN,
184 .chan = { { .pin = GPIO_PIN(PORT_D, 12), .cc_chan = 0},
185 { .pin = GPIO_PIN(PORT_D, 13), .cc_chan = 1},
186 { .pin = GPIO_PIN(PORT_D, 14), .cc_chan = 2},
187 { .pin = GPIO_PIN(PORT_D, 15), .cc_chan = 3} },
188 .af = GPIO_AF2,
189 .bus = APB1
190 },
191};
192#define PWM_NUMOF ARRAY_SIZE(pwm_config)
194
195#ifdef __cplusplus
196}
197#endif
198
@ PORT_B
port B
Definition periph_cpu.h:44
@ PORT_G
port G
Definition periph_cpu.h:49
@ PORT_C
port C
Definition periph_cpu.h:45
@ PORT_F
port F
Definition periph_cpu.h:48
@ PORT_E
port E
Definition periph_cpu.h:47
@ PORT_A
port A
Definition periph_cpu.h:43
@ PORT_D
port D
Definition periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5 and TIM2.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:99
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:100
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:103
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:105
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
ADC device configuration.
Definition periph_cpu.h:374
DMA configuration.
Definition cpu_dma.h:28
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:333
UART device configuration.
Definition periph_cpu.h:214