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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2017 Inria
3 * SPDX-License-Identifier: LGPL-2.1-only
4 */
5
6#pragma once
7
17
18/* This board provides an LSE */
19#ifndef CONFIG_BOARD_HAS_LSE
20#define CONFIG_BOARD_HAS_LSE 1
21#endif
22
23/* This board provides an HSE */
24#ifndef CONFIG_BOARD_HAS_HSE
25#define CONFIG_BOARD_HAS_HSE 1
26#endif
27
28#include "periph_cpu.h"
29#include "clk_conf.h"
30#include "cfg_i2c1_pb8_pb9.h"
32#include "cfg_usb_otg_fs.h"
33#include "mii.h"
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
43static const dma_conf_t dma_config[] = {
44 { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
45 { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
46 { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */
47};
48
49#define DMA_0_ISR isr_dma2_stream3
50#define DMA_1_ISR isr_dma2_stream2
51#define DMA_2_ISR isr_dma2_stream0
52
53#define DMA_NUMOF ARRAY_SIZE(dma_config)
55
60static const uart_conf_t uart_config[] = {
61 {
62 .dev = USART3,
63 .rcc_mask = RCC_APB1ENR_USART3EN,
64 .rx_pin = GPIO_PIN(PORT_D, 9),
65 .tx_pin = GPIO_PIN(PORT_D, 8),
66 .rx_af = GPIO_AF7,
67 .tx_af = GPIO_AF7,
68 .bus = APB1,
69 .irqn = USART3_IRQn,
70#ifdef MODULE_PERIPH_DMA
71 .dma = DMA_STREAM_UNDEF,
72 .dma_chan = UINT8_MAX,
73#endif
74 },
75 {
76 .dev = USART6,
77 .rcc_mask = RCC_APB2ENR_USART6EN,
78 .rx_pin = GPIO_PIN(PORT_G, 9),
79 .tx_pin = GPIO_PIN(PORT_G, 14),
80 .rx_af = GPIO_AF8,
81 .tx_af = GPIO_AF8,
82 .bus = APB2,
83 .irqn = USART6_IRQn,
84#ifdef MODULE_PERIPH_DMA
85 .dma = DMA_STREAM_UNDEF,
86 .dma_chan = UINT8_MAX,
87#endif
88 },
89 {
90 .dev = USART2,
91 .rcc_mask = RCC_APB1ENR_USART2EN,
92 .rx_pin = GPIO_PIN(PORT_D, 6),
93 .tx_pin = GPIO_PIN(PORT_D, 5),
94 .rx_af = GPIO_AF7,
95 .tx_af = GPIO_AF7,
96 .bus = APB1,
97 .irqn = USART2_IRQn,
98#ifdef MODULE_PERIPH_DMA
99 .dma = DMA_STREAM_UNDEF,
100 .dma_chan = UINT8_MAX,
101#endif
102 },
103};
104
105#define UART_0_ISR (isr_usart3)
106#define UART_1_ISR (isr_usart6)
107#define UART_2_ISR (isr_usart2)
108
109#define UART_NUMOF ARRAY_SIZE(uart_config)
111
116static const pwm_conf_t pwm_config[] = {
117 {
118 .dev = TIM1,
119 .rcc_mask = RCC_APB2ENR_TIM1EN,
120 .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
121 { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
122 { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
123 { .pin = GPIO_UNDEF, .cc_chan = 0} },
124 .af = GPIO_AF1,
125 .bus = APB2
126 },
127 {
128 .dev = TIM4,
129 .rcc_mask = RCC_APB1ENR_TIM4EN,
130 .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
131 { .pin = GPIO_UNDEF, .cc_chan = 0},
132 { .pin = GPIO_UNDEF, .cc_chan = 0},
133 { .pin = GPIO_UNDEF, .cc_chan = 0} },
134 .af = GPIO_AF2,
135 .bus = APB1
136 },
137};
138
139#define PWM_NUMOF ARRAY_SIZE(pwm_config)
141
146static const spi_conf_t spi_config[] = {
147 {
148 .dev = SPI1,
149 .mosi_pin = GPIO_PIN(PORT_A, 7),
150 .miso_pin = GPIO_PIN(PORT_A, 6),
151 .sclk_pin = GPIO_PIN(PORT_A, 5),
152 .cs_pin = GPIO_UNDEF,
153 .mosi_af = GPIO_AF5,
154 .miso_af = GPIO_AF5,
155 .sclk_af = GPIO_AF5,
156 .cs_af = GPIO_AF5,
157 .rccmask = RCC_APB2ENR_SPI1EN,
158 .apbbus = APB2,
159#ifdef MODULE_PERIPH_DMA
160 .tx_dma = 0,
161 .tx_dma_chan = 3,
162 .rx_dma = 1,
163 .rx_dma_chan = 3,
164#endif
165 }
166};
167
168#define SPI_NUMOF ARRAY_SIZE(spi_config)
170
181static const adc_conf_t adc_config[] = {
182 {GPIO_PIN(PORT_A, 3), 2, 3},
183 {GPIO_PIN(PORT_C, 0), 2, 10},
184 {GPIO_PIN(PORT_C, 3), 2, 13},
185 {GPIO_PIN(PORT_F, 3), 2, 9},
186 {GPIO_PIN(PORT_F, 5), 2, 15},
187 {GPIO_PIN(PORT_F, 10), 2, 8},
188 {GPIO_UNDEF, 0, 18}, /* VBAT */
189};
190
191#define VBAT_ADC ADC_LINE(6)
192#define ADC_NUMOF ARRAY_SIZE(adc_config)
194
199static const eth_conf_t eth_config = {
200 .mode = RMII,
202 .dma = 2,
203 .dma_chan = 8,
204 .phy_addr = 0x00,
205 .pins = {
206 GPIO_PIN(PORT_G, 13),
207 GPIO_PIN(PORT_B, 13),
208 GPIO_PIN(PORT_G, 11),
209 GPIO_PIN(PORT_C, 4),
210 GPIO_PIN(PORT_C, 5),
211 GPIO_PIN(PORT_A, 7),
212 GPIO_PIN(PORT_C, 1),
213 GPIO_PIN(PORT_A, 2),
214 GPIO_PIN(PORT_A, 1),
215 }
216};
217
218#define ETH_DMA_ISR isr_dma2_stream0
220
221#ifdef __cplusplus
222}
223#endif
224
@ PORT_B
port B
Definition periph_cpu.h:47
@ PORT_G
port G
Definition periph_cpu.h:52
@ PORT_C
port C
Definition periph_cpu.h:48
@ PORT_F
port F
Definition periph_cpu.h:51
@ PORT_E
port E
Definition periph_cpu.h:50
@ PORT_A
port A
Definition periph_cpu.h:46
@ PORT_D
port D
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5 and TIM2.
Common configuration for STM32 OTG FS peripheral.
@ RMII
Configuration for RMII.
Definition cpu_eth.h:36
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
#define MII_BMCR_FULL_DPLX
Set for full duplex.
Definition mii.h:68
#define MII_BMCR_SPEED_100
Set speed to 100 Mbps.
Definition mii.h:72
Interface definition for MII/RMII h.
ADC device configuration.
Definition periph_cpu.h:377
DMA configuration.
Definition cpu_dma.h:31
Ethernet Peripheral configuration.
Definition cpu_eth.h:43
PWM device configuration.
SPI device configuration.
Definition periph_cpu.h:336
UART device configuration.
Definition periph_cpu.h:217