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periph_conf.h
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1/*
2 * Copyright (C) 2019 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* This board provides an LSE */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27/* This board provides an HSE */
28#ifndef CONFIG_BOARD_HAS_HSE
29#define CONFIG_BOARD_HAS_HSE 1
30#endif
31
32/* The HSE provides a 25MHz clock */
33#ifndef CONFIG_CLOCK_HSE
34#define CONFIG_CLOCK_HSE MHZ(25)
35#endif
36
37#include "periph_cpu.h"
38#include "clk_conf.h"
39#include "cfg_rtt_default.h"
40#if defined(MODULE_PERIPH_USBDEV_HS_UTMI)
42#else
43#include "cfg_usb_otg_fs.h"
44#endif
45#include "lcd_fmc.h"
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
55static const timer_conf_t timer_config[] = {
56 {
57 .dev = TIM2,
58 .max = 0xffffffff,
59 .rcc_mask = RCC_APB1ENR_TIM2EN,
60 .bus = APB1,
61 .irqn = TIM2_IRQn
62 }
63};
64
65#define TIMER_0_ISR isr_tim2
66
67#define TIMER_NUMOF ARRAY_SIZE(timer_config)
74static const uart_conf_t uart_config[] = {
75 {
76 .dev = USART6,
77 .rcc_mask = RCC_APB2ENR_USART6EN,
78 .rx_pin = GPIO_PIN(PORT_C, 6),
79 .tx_pin = GPIO_PIN(PORT_C, 7),
80 .rx_af = GPIO_AF8,
81 .tx_af = GPIO_AF8,
82 .bus = APB2,
83 .irqn = USART6_IRQn,
84#ifdef MODULE_PERIPH_UART_HW_FC
85 .cts_pin = GPIO_UNDEF,
86 .rts_pin = GPIO_UNDEF,
87 .cts_af = GPIO_AF8,
88 .rts_af = GPIO_AF8,
89#endif
90 },
91 { /* Arduino connector (D0/D1) */
92 .dev = USART2,
93 .rcc_mask = RCC_APB1ENR_USART2EN,
94 .rx_pin = GPIO_PIN(PORT_A, 3),
95 .tx_pin = GPIO_PIN(PORT_A, 2),
96 .rx_af = GPIO_AF7,
97 .tx_af = GPIO_AF7,
98 .bus = APB1,
99 .irqn = USART2_IRQn,
100#ifdef MODULE_PERIPH_UART_HW_FC
101 .cts_pin = GPIO_UNDEF,
102 .rts_pin = GPIO_UNDEF,
103 .cts_af = GPIO_AF8,
104 .rts_af = GPIO_AF8,
105#endif
106 },
107 { /* PMOD connector */
108 .dev = UART7,
109 .rcc_mask = RCC_APB1ENR_UART7EN,
110 .rx_pin = GPIO_PIN(PORT_F, 6),
111 .tx_pin = GPIO_PIN(PORT_F, 7),
112 .rx_af = GPIO_AF8,
113 .tx_af = GPIO_AF8,
114 .bus = APB1,
115 .irqn = UART7_IRQn,
116#ifdef MODULE_PERIPH_UART_HW_FC
117 .cts_pin = GPIO_PIN(PORT_F, 9),
118 .rts_pin = GPIO_PIN(PORT_F, 8),
119 .cts_af = GPIO_AF8,
120 .rts_af = GPIO_AF8,
121#endif
122 },
123 { /* ESP-01 connector */
124 .dev = UART5,
125 .rcc_mask = RCC_APB1ENR_UART5EN,
126 .rx_pin = GPIO_PIN(PORT_D, 2),
127 .tx_pin = GPIO_PIN(PORT_C, 12),
128 .rx_af = GPIO_AF8,
129 .tx_af = GPIO_AF8,
130 .bus = APB1,
131 .irqn = UART5_IRQn,
132#ifdef MODULE_PERIPH_UART_HW_FC
133 .cts_pin = GPIO_UNDEF,
134 .rts_pin = GPIO_UNDEF,
135 .cts_af = GPIO_AF8,
136 .rts_af = GPIO_AF8,
137#endif
138 },
139};
140
141#define UART_0_ISR (isr_usart6)
142#define UART_1_ISR (isr_usart2)
143#define UART_2_ISR (isr_uart4)
144#define UART_3_ISR (isr_uart7)
145#define UART_4_ISR (isr_uart5)
146
147#define UART_NUMOF ARRAY_SIZE(uart_config)
154static const i2c_conf_t i2c_config[] = {
155 { /* Shared between Arduino D14/D15 and STMOD+ connector */
156 .dev = I2C2,
157 .speed = I2C_SPEED_NORMAL,
158 .scl_pin = GPIO_PIN(PORT_H, 4),
159 .sda_pin = GPIO_PIN(PORT_H, 5),
160 .scl_af = GPIO_AF4,
161 .sda_af = GPIO_AF4,
162 .bus = APB1,
163 .rcc_mask = RCC_APB1ENR_I2C2EN,
164 .rcc_sw_mask = RCC_DCKCFGR2_I2C2SEL_1,
165 .irqn = I2C2_ER_IRQn,
166 },
167 { /* Connected to touchscreen controller */
168 .dev = I2C3,
169 .speed = I2C_SPEED_NORMAL,
170 .scl_pin = GPIO_PIN(PORT_A, 8),
171 .sda_pin = GPIO_PIN(PORT_H, 8),
172 .scl_af = GPIO_AF4,
173 .sda_af = GPIO_AF4,
174 .bus = APB1,
175 .rcc_mask = RCC_APB1ENR_I2C3EN,
176 .rcc_sw_mask = RCC_DCKCFGR2_I2C3SEL_1,
177 .irqn = I2C3_ER_IRQn,
178 },
179 {
180 .dev = I2C1,
181 .speed = I2C_SPEED_NORMAL,
182 .scl_pin = GPIO_PIN(PORT_B, 8),
183 .sda_pin = GPIO_PIN(PORT_B, 9),
184 .scl_af = GPIO_AF4,
185 .sda_af = GPIO_AF4,
186 .bus = APB1,
187 .rcc_mask = RCC_APB1ENR_I2C1EN,
188 .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1,
189 .irqn = I2C1_ER_IRQn,
190 },
191};
192
193#define I2C_0_ISR isr_i2c2_er
194#define I2C_1_ISR isr_i2c3_er
195#define I2C_2_ISR isr_i2c1_er
196
197#define I2C_NUMOF ARRAY_SIZE(i2c_config)
204static const spi_conf_t spi_config[] = {
205 { /* Arduino connector */
206 .dev = SPI1,
207 .mosi_pin = GPIO_PIN(PORT_B, 5),
208 .miso_pin = GPIO_PIN(PORT_B, 4),
209 .sclk_pin = GPIO_PIN(PORT_A, 5),
210 .cs_pin = SPI_CS_UNDEF,
211 .mosi_af = GPIO_AF5,
212 .miso_af = GPIO_AF5,
213 .sclk_af = GPIO_AF5,
214 .cs_af = GPIO_AF5,
215 .rccmask = RCC_APB2ENR_SPI1EN,
216 .apbbus = APB2
217 },
218 { /* PMOD connector */
219 .dev = SPI2,
220 .mosi_pin = GPIO_PIN(PORT_I, 3),
221 .miso_pin = GPIO_PIN(PORT_I, 2),
222 .sclk_pin = GPIO_PIN(PORT_I, 1),
223 .cs_pin = GPIO_PIN(PORT_I, 0),
224 .mosi_af = GPIO_AF5,
225 .miso_af = GPIO_AF5,
226 .sclk_af = GPIO_AF5,
227 .cs_af = GPIO_AF5,
228 .rccmask = RCC_APB1ENR_SPI2EN,
229 .apbbus = APB1
230 },
231};
232
233#define SPI_NUMOF ARRAY_SIZE(spi_config)
244static const fmc_conf_t fmc_config = {
245 .bus = AHB3,
246 .rcc_mask = RCC_AHB3ENR_FMCEN,
247#if MODULE_PERIPH_FMC_NOR_SRAM
248 .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* PSRAM_NE1 signal, subbank 1 */
249 .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 2 */
250 .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* LCD_PSRAM_NOE */
251 .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* LCD_PSRAM_NWE signal */
252 .addr = {
253 { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 / LCD_RS signal */
254 { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
255 { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
256 { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
257 { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
258 { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
259 { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
260 { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
261 { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
262 { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
263 { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
264 { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
265 { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
266 { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
267 { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
268 { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
269 { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
270 { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
271 },
272#endif
273 .data = {
274 { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D0 signal */
275 { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D1 signal */
276 { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* LCD_PSRAM_D2 signal */
277 { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* LCD_PSRAM_D3 signal */
278 { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* LCD_PSRAM_D4 signal */
279 { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D5 signal */
280 { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D6 signal */
281 { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D7 signal */
282#if MODULE_PERIPH_FMC_16BIT
283 { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* LCD_PSRAM_D8 signal */
284 { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* LCD_PSRAM_D9 signal */
285 { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* LCD_PSRAM_D10 signal */
286 { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* LCD_PSRAM_D11 signal */
287 { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* LCD_PSRAM_D12 signal */
288 { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* LCD_PSRAM_D13 signal */
289 { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* LCD_PSRAM_D14 signal */
290 { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* LCD_PSRAM_D15 signal */
291#endif
292 },
293 .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
294 .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
295};
296
311 /* bank 1, subbank 1 is used for PSRAM with asynchronuous
312 * access in Mode 1, i.e. write timings are not used */
313 {
314 .bank = FMC_BANK_1,
315 .mem_type = FMC_SRAM,
316 .data_width = FMC_BUS_WIDTH_16BIT,
317 .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
318 .size = KiB(512), /* Size in byte, 256K x 16 bit */
319 .nor_sram = {
320 .sub_bank = 1,
321 .ext_mode = false, /* Mode 1 used, no separate w_timing */
322 /* timings for IS66WV51216EBLL-55BLI
323 @216 MHz AHB clock */
324 .r_timing = { .addr_setup = 13, /* t_AA = max 60 ns (13 HCLKs a 4.63 ns) */
325 .data_setup = 6, /* t_SD = min 25 ns (6 HCLKs a 4.63 ns) */
326 .bus_turnaround = 3, }, /* 3 HCLKs a 4.63 ns */
327 },
328 },
329 /* bank 1, subbank 2 is used for LCD with asynchronuous
330 * access in Mode 1, i.e. write timings are not used */
331 {
332 .bank = FMC_BANK_1,
333 .mem_type = FMC_SRAM,
334 .data_width = FMC_BUS_WIDTH_16BIT,
335 .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
336 .size = 4, /* 1 word for command @ 0x64000000 and
337 1 word for data @ 0x64000001 */
338 .nor_sram = {
339 .sub_bank = 2,
340 .ext_mode = false, /* Mode 1 used, no separate w_timing */
341 /* timing requirements for ST7789H2:
342 - t_AST min 0 ns (Address setup time)
343 - t_DST min 10 ns (Data setup time)
344 - t_WRL min 15 ns (WE LOW time)
345 - t_WRH min 15 ns (WE HIGH time)
346 - t_WRC min 66 ns (WE cycle time) */
347 .r_timing = { .addr_setup = 2, /* t_AST = 10 ns (2 HCLKs a 4.63 ns) */
348 .data_setup = 8, /* t_DST = 37 ns (8 HCLKs a 4.63 ns) */
349 .bus_turnaround = 5, }, /* t_WRH = 23 ns (5 HCLKs a 4.63 ns) */
350 },
351 },
352};
353
357#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
363static const lcd_fmc_desc_t lcd_fmc_desc[] = {
364 {
365 .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
366 .cmd_offset = 0x0, /* address 0x64000000 (offset 0x0) used for commands */
367 .data_offset = 0x2, /* address 0x64000002 (offset 0x2) used for commands */
368 }
369};
370
377#define LCD_FMC_NUMOF 1
378
379#ifdef __cplusplus
380}
381#endif
382
383#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_G
port G
Definition periph_cpu.h:53
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ PORT_H
port H
Definition periph_cpu.h:52
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
static const fmc_conf_t fmc_config
FMC controller configuration.
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Common configuration for STM32 OTG FS peripheral.
Common configuration for STM32 OTG HS peripheral with internal UTMI HS PHY.
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:111
@ GPIO_AF12
use alternate function 12
Definition cpu_gpio.h:115
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition cpu_fmc.h:75
@ FMC_SRAM
SRAM.
Definition cpu_fmc.h:341
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition cpu_fmc.h:353
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition cpu_fmc.h:321
Bank configuration structure.
Definition cpu_fmc.h:360
fmc_bank_t bank
Bank1 .
Definition cpu_fmc.h:361
FMC peripheral configuration.
Definition cpu_fmc.h:278
uint8_t bus
AHB/APB bus.
Definition cpu_fmc.h:279
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
Descriptor of the FMC bank used for a LCD.
Definition lcd_fmc.h:49
const fmc_bank_conf_t * bank
FMC bank config used for the LCD.
Definition lcd_fmc.h:50
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219
#define KiB(x)
A macro to return the bytes in x KiB.
Definition units.h:29