RISCV CLIC interrupt controller definitions.
More...
RISCV CLIC interrupt controller definitions.
RISCV implementations using this peripheral must define the CLIC_BASE_ADDR
, in order to use the PLIC as interrupt controller. Also required is CLIC_NUM_INTERRUPTS.
- Author
- Koen Zandberg koen@.nosp@m.berg.nosp@m.zand..nosp@m.net
Definition in file clic.h.
#include "cpu_conf.h"
Go to the source code of this file.
◆ clic_isr_cb_t
typedef void(* clic_isr_cb_t) (unsigned irq) |
CLIC callback declaration.
- Parameters
-
Definition at line 35 of file clic.h.
◆ __attribute()
struct __attribute |
( |
(packed) |
| ) |
|
RISC-V CLIC per interrupt configuration registers.
< Interrupt pending
< Interrupt enable
< Interrupt attributes
< Interrupt control
Definition at line 35 of file clic.h.
◆ clic_disable_interrupt()
void clic_disable_interrupt |
( |
unsigned |
irq | ) |
|
Disable a single interrupt.
- Parameters
-
irq | Interrupt number to disable |
◆ clic_enable_interrupt()
void clic_enable_interrupt |
( |
unsigned |
irq, |
|
|
unsigned |
priority |
|
) |
| |
Enable a single interrupt.
- Parameters
-
irq | Interrupt number to enable |
priority | Priority level to configure |
◆ clic_set_handler()
Set the handler for an interrupt.
- Parameters
-
irq | Interrupt number to configure |
cb | Callback handler to configure |
◆ clic_set_priority()
void clic_set_priority |
( |
unsigned |
irq, |
|
|
unsigned |
priority |
|
) |
| |
Set the priority of an interrupt.
- Parameters
-
irq | Interrupt number to configure |
priority | Priority level to configure |
◆ clic_clicint_t