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periph_conf.h
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1/*
2 * SPDX-FileCopyrightText: 2018 Inria
3 * SPDX-FileCopyrightText: 2023 Gunar Schorcht
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20/* Add specific clock configuration (HSE, LSE) for this board here */
21#ifndef CONFIG_BOARD_HAS_LSE
22#define CONFIG_BOARD_HAS_LSE 1
23#endif
24
25#include "periph_cpu.h"
26#include "clk_conf.h"
27#include "cfg_rtt_default.h"
28#include "cfg_usb_otg_fs.h"
29#include "lcd_fmc.h"
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
39static const dma_conf_t dma_config[] = {
40 { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX */
41 { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
42 { .stream = 3 }, /* DMA1 Channel 4 - SPI2_RX / USART1_TX */
43 { .stream = 4 }, /* DMA1 Channel 5 - SPI2_TX */
44 { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
45 { .stream = 13 }, /* DMA2 Channel 6 - LPUART1_TX */
46 { .stream = 11 }, /* DMA2 Channel 4 - SDMMC1 */
47};
48
49#define DMA_0_ISR isr_dma1_channel2
50#define DMA_1_ISR isr_dma1_channel3
51#define DMA_2_ISR isr_dma1_channel4
52#define DMA_3_ISR isr_dma1_channel5
53#define DMA_4_ISR isr_dma1_channel7
54#define DMA_5_ISR isr_dma2_channel6
55#define DMA_6_ISR isr_dma2_channel4
56
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
59
95
96static const adc_conf_t adc_config[] = {
97 { .pin = GPIO_PIN(PORT_C, 4), .dev = 0, .chan = 13 }, /* A0, ADC12_IN13 */
98 { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* A1, ADC123_IN2 */
99 { .pin = GPIO_PIN(PORT_C, 3), .dev = 0, .chan = 4 }, /* A2, ADC123_IN4 */
100 { .pin = GPIO_PIN(PORT_F, 10), .dev = 2, .chan = 13 }, /* A3, ADC3_IN13 */
101 { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6 }, /* A4, ADC12_IN6, SB26 closed */
102 { .pin = GPIO_PIN(PORT_C, 0), .dev = 1, .chan = 13 }, /* A5, ADC12_IN13, SB28 closed */
103 { .pin = GPIO_UNDEF, .dev = 0, .chan = 0 }, /* V_REFINT, ADC1_IN0 */
104 { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, /* V_BAT, ADC1_IN18 */
105#if !MODULE_PERIPH_DAC
106 { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9 }, /* STMOD+_ADC, ADC12_IN9 */
107#else
108 { .pin = GPIO_UNDEF, .dev = 1, .chan = 17 }, /* DAC1, ADC2_IN17 */
109#endif
110};
111
115#define ADC_NUMOF ARRAY_SIZE(adc_config)
116
120#define VBAT_ADC ADC_LINE(7)
121
125#define VREFINT_ADC ADC_LINE(6)
126
135#ifndef VREFBUF_ENABLE
136#define VREFBUF_ENABLE (1)
137#endif
138
140
150static const dac_conf_t dac_config[] = {
151 { GPIO_PIN(PORT_A, 4), .chan = 0 }, /* STMod+_ADC pin */
152#if !MODULE_PERIPH_SPI
153 { GPIO_PIN(PORT_A, 5), .chan = 1 }, /* Arduino D13, conflicts with SPI_DEV(0) */
154#endif
155};
156
160#define DAC_NUMOF ARRAY_SIZE(dac_config)
162
167
171static const fmc_conf_t fmc_config = {
172 .bus = AHB3,
173 .rcc_mask = RCC_AHB3ENR_FMCEN,
174#if MODULE_PERIPH_FMC_NOR_SRAM
175 .ne1_pin = { .pin = GPIO_PIN(PORT_D, 7), .af = GPIO_AF12, }, /* LCD_NE signal, subbank 1 */
176 .ne2_pin = { .pin = GPIO_PIN(PORT_G, 9), .af = GPIO_AF12, }, /* PSRAM_NE signal, subbank 2 */
177 .noe_pin = { .pin = GPIO_PIN(PORT_D, 4), .af = GPIO_AF12, }, /* PSRAM/LCD_OE signal (OE) */
178 .nwe_pin = { .pin = GPIO_PIN(PORT_D, 5), .af = GPIO_AF12, }, /* PSRAM/LCD_WE signal (WE) */
179 .addr = {
180 { .pin = GPIO_PIN(PORT_F, 0), .af = GPIO_AF12, }, /* PSRAM_A0 signal */
181 { .pin = GPIO_PIN(PORT_F, 1), .af = GPIO_AF12, }, /* PSRAM_A1 signal */
182 { .pin = GPIO_PIN(PORT_F, 2), .af = GPIO_AF12, }, /* PSRAM_A2 signal */
183 { .pin = GPIO_PIN(PORT_F, 3), .af = GPIO_AF12, }, /* PSRAM_A3 signal */
184 { .pin = GPIO_PIN(PORT_F, 4), .af = GPIO_AF12, }, /* PSRAM_A4 signal */
185 { .pin = GPIO_PIN(PORT_F, 5), .af = GPIO_AF12, }, /* PSRAM_A5 signal */
186 { .pin = GPIO_PIN(PORT_F, 12), .af = GPIO_AF12, }, /* PSRAM_A6 signal */
187 { .pin = GPIO_PIN(PORT_F, 13), .af = GPIO_AF12, }, /* PSRAM_A7 signal */
188 { .pin = GPIO_PIN(PORT_F, 14), .af = GPIO_AF12, }, /* PSRAM_A8 signal */
189 { .pin = GPIO_PIN(PORT_F, 15), .af = GPIO_AF12, }, /* PSRAM_A9 signal */
190 { .pin = GPIO_PIN(PORT_G, 0), .af = GPIO_AF12, }, /* PSRAM_A10 signal */
191 { .pin = GPIO_PIN(PORT_G, 1), .af = GPIO_AF12, }, /* PSRAM_A11 signal */
192 { .pin = GPIO_PIN(PORT_G, 2), .af = GPIO_AF12, }, /* PSRAM_A12 signal */
193 { .pin = GPIO_PIN(PORT_G, 3), .af = GPIO_AF12, }, /* PSRAM_A13 signal */
194 { .pin = GPIO_PIN(PORT_G, 4), .af = GPIO_AF12, }, /* PSRAM_A14 signal */
195 { .pin = GPIO_PIN(PORT_G, 5), .af = GPIO_AF12, }, /* PSRAM_A15 signal */
196 { .pin = GPIO_PIN(PORT_D, 11), .af = GPIO_AF12, }, /* PSRAM_A16 signal */
197 { .pin = GPIO_PIN(PORT_D, 12), .af = GPIO_AF12, }, /* PSRAM_A17 signal */
198 { .pin = GPIO_PIN(PORT_D, 13), .af = GPIO_AF12, }, /* PSRAM_A18 / LCD_RS signal */
199 },
200#endif
201 .data = {
202 { .pin = GPIO_PIN(PORT_D, 14), .af = GPIO_AF12, }, /* PSRAM_D0 / LCD_D0 signal */
203 { .pin = GPIO_PIN(PORT_D, 15), .af = GPIO_AF12, }, /* PSRAM_D1 / LCD_D1 signal */
204 { .pin = GPIO_PIN(PORT_D, 0), .af = GPIO_AF12, }, /* PSRAM_D2 / LCD_D2 signal */
205 { .pin = GPIO_PIN(PORT_D, 1), .af = GPIO_AF12, }, /* PSRAM_D3 / LCD_D3 signal */
206 { .pin = GPIO_PIN(PORT_E, 7), .af = GPIO_AF12, }, /* PSRAM_D4 / LCD_D4 signal */
207 { .pin = GPIO_PIN(PORT_E, 8), .af = GPIO_AF12, }, /* PSRAM_D5 / LCD_D5 signal */
208 { .pin = GPIO_PIN(PORT_E, 9), .af = GPIO_AF12, }, /* PSRAM_D6 / LCD_D6 signal */
209 { .pin = GPIO_PIN(PORT_E, 10), .af = GPIO_AF12, }, /* PSRAM_D7 / LCD_D7 signal */
210#if MODULE_PERIPH_FMC_16BIT
211 { .pin = GPIO_PIN(PORT_E, 11), .af = GPIO_AF12, }, /* PSRAM_D8 / LCD_D8 signal */
212 { .pin = GPIO_PIN(PORT_E, 12), .af = GPIO_AF12, }, /* PSRAM_D9 / LCD_D9 signal */
213 { .pin = GPIO_PIN(PORT_E, 13), .af = GPIO_AF12, }, /* PSRAM_D10 / LCD_D10 signal */
214 { .pin = GPIO_PIN(PORT_E, 14), .af = GPIO_AF12, }, /* PSRAM_D11 / LCD_D11 signal */
215 { .pin = GPIO_PIN(PORT_E, 15), .af = GPIO_AF12, }, /* PSRAM_D12 / LCD_D12 signal */
216 { .pin = GPIO_PIN(PORT_D, 8), .af = GPIO_AF12, }, /* PSRAM_D13 / LCD_D13 signal */
217 { .pin = GPIO_PIN(PORT_D, 9), .af = GPIO_AF12, }, /* PSRAM_D14 / LCD_D14 signal */
218 { .pin = GPIO_PIN(PORT_D, 10), .af = GPIO_AF12, }, /* PSRAM_D15 / LCD_D15 signal */
219#endif
220 },
221 .nbl0_pin = { .pin = GPIO_PIN(PORT_E, 0), .af = GPIO_AF12, }, /* PSRAM_NBL0 signal (LB) */
222 .nbl1_pin = { .pin = GPIO_PIN(PORT_E, 1), .af = GPIO_AF12, }, /* PSRAM_NBL1 signal (UB) */
223};
224
235static const fmc_bank_conf_t fmc_bank_config[] = {
236 /* bank 1, subbank 2 is used for PSRAM with asynchronuous
237 * access in Mode 1, i.e. write timings are not used */
238 {
239 .bank = FMC_BANK_1,
240 .mem_type = FMC_SRAM,
241 .data_width = FMC_BUS_WIDTH_16BIT,
242 .address = 0x64000000, /* Bank 1, subbank 2 is mapped to 0x64000000 */
243 .size = MiB(1), /* Size in Mbyte, 512K x 16 bit */
244 .nor_sram = {
245 .sub_bank = 2,
246 .ext_mode = false, /* Mode 1 used, no separate w_timing */
247 /* timings for IS66WV51216EBLL-70BLI */
248 .r_timing = { .addr_setup = 6, /* t_AA = 70 ns (6 HCLKs a 12.5 ns) */
249 .data_setup = 2, /* t_SD = 30 ns (3 HCLKs a 12.5 ns) */
250 .bus_turnaround = 1, }, /* 1 HCLK a 12.5 ns */
251 },
252 },
253 /* bank 1, subbank 1 is used for LCD with asynchronuous
254 * access in Mode 1, i.e. write timings are not used */
255 {
256 .bank = FMC_BANK_1,
257 .mem_type = FMC_SRAM,
258 .data_width = FMC_BUS_WIDTH_16BIT,
259 .address = 0x60000000, /* Bank 1, subbank 1 is mapped to 0x60000000 */
260 .size = 2, /* 1 word for command @ 0x60000000 and
261 1 word for data @ 0x60080000 */
262 .nor_sram = {
263 .sub_bank = 1,
264 .ext_mode = false, /* Mode 1 used, no separate w_timing */
265 /* timing requirements for ST7789H2:
266 - t_AST min 0 ns (Address setup time)
267 - t_DST min 10 ns (Data setup time)
268 - t_WRL min 15 ns (WE LOW time)
269 - t_WRH min 15 ns (WE HIGH time)
270 - t_WRC min 66 ns (WE cycle time) */
271 .r_timing = { .addr_setup = 1, /* t_AST = 12 ns (1 HCLKs a 12.5 ns) */
272 .data_setup = 3, /* t_DST = 37 ns (3 HCLKs a 12.5 ns) */
273 .bus_turnaround = 2, }, /* t_WRH = 25 ns (2 HCLKs a 12.5 ns) */
274 },
275 },
276};
277
281#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
282
286static const lcd_fmc_desc_t lcd_fmc_desc[] = {
287 {
288 .bank = FMC_BANK_CONFIG(1), /* second bank (fmc_bank_config[1]) is used */
289 .cmd_offset = 0x0, /* address 0x60000000 (offset 0x00000) used for commands */
290 .data_offset = 0x80000, /* address 0x60080000 (offset 0x80000) used for data */
291 }
292};
293
300#define LCD_FMC_NUMOF 1
301
303
311static const i2c_conf_t i2c_config[] = {
312 { /* Shared between Arduino D14/D15 and STMod+ connector */
313 .dev = I2C1,
314 .speed = I2C_SPEED_NORMAL,
315 .scl_pin = GPIO_PIN(PORT_B, 8),
316 .sda_pin = GPIO_PIN(PORT_B, 7),
317 .scl_af = GPIO_AF4,
318 .sda_af = GPIO_AF4,
319 .bus = APB1,
320 .rcc_mask = RCC_APB1ENR1_I2C1EN,
321 .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
322 .irqn = I2C1_ER_IRQn,
323 },
324 { /* Multi Function eXpander (MFX_x) I2C Address 0x42,
325 * Stereo Codec Cirrus Logic CS42L51-CNZ (CODEC_x), I2C Address 0x4a (AD0 = 0)
326 * Capacitive Touch Panel (CTP_x) FT6206, I2C Address 0x38
327 * Digital Camera Module (DCMI_x),
328 */
329 .dev = I2C2,
330 .speed = I2C_SPEED_NORMAL,
331 .scl_pin = GPIO_PIN(PORT_H, 4),
332 .sda_pin = GPIO_PIN(PORT_B, 14),
333 .scl_af = GPIO_AF4,
334 .sda_af = GPIO_AF4,
335 .bus = APB1,
336 .rcc_mask = RCC_APB1ENR1_I2C2EN,
337 .rcc_sw_mask = RCC_CCIPR_I2C2SEL_1, /* HSI (16 MHz) */
338 .irqn = I2C2_ER_IRQn,
339 },
340};
341
342#define I2C_0_ISR isr_i2c1_er
343#define I2C_1_ISR isr_i2c2_er
344
345#define I2C_NUMOF ARRAY_SIZE(i2c_config)
347
360static const pwm_conf_t pwm_config[] = {
361 {
362 .dev = TIM8,
363 .rcc_mask = RCC_APB2ENR_TIM8EN,
364 .chan = { { .pin = GPIO_PIN(PORT_H, 15), .cc_chan = 6}, /* D3, TIM8_CH3N */
365 { .pin = GPIO_PIN(PORT_I, 6), .cc_chan = 1}, /* D6, TIM8_CH2 */
366 { .pin = GPIO_PIN(PORT_H, 13), .cc_chan = 4}, /* D9, TIM8_CH1N */
367 { .pin = GPIO_UNDEF, .cc_chan = 0} },
368 .af = GPIO_AF3,
369 .bus = APB2
370 },
371 {
372 .dev = TIM4,
373 .rcc_mask = RCC_APB1ENR1_TIM4EN,
374 .chan = { { .pin = GPIO_PIN(PORT_B, 9), .cc_chan = 3}, /* D5, TIM4_CH4 */
375 { .pin = GPIO_UNDEF, .cc_chan = 0},
376 { .pin = GPIO_UNDEF, .cc_chan = 0},
377 { .pin = GPIO_UNDEF, .cc_chan = 0} },
378 .af = GPIO_AF2,
379 .bus = APB1
380 },
381 {
382 .dev = TIM5,
383 .rcc_mask = RCC_APB1ENR1_TIM5EN,
384 .chan = { { .pin = GPIO_PIN(PORT_A, 0), .cc_chan = 0}, /* STMOD+_PWM, TIM5_CH1 */
385 { .pin = GPIO_UNDEF, .cc_chan = 0},
386 { .pin = GPIO_UNDEF, .cc_chan = 0},
387 { .pin = GPIO_UNDEF, .cc_chan = 0} },
388 .af = GPIO_AF2,
389 .bus = APB1
390 },
391};
392
393#define PWM_NUMOF ARRAY_SIZE(pwm_config)
395
400
404static const sdmmc_conf_t sdmmc_config[] = {
405 {
406 .dev = SDMMC1,
407 .bus = APB2,
408 .rcc_mask = RCC_APB2ENR_SDMMC1EN,
409 .cd = GPIO_UNDEF, /* CD is connected to MFX GPIO8 */
410 .clk = { GPIO_PIN(PORT_C, 12), GPIO_AF12 },
411 .cmd = { GPIO_PIN(PORT_D, 2), GPIO_AF12 },
412 .dat0 = { GPIO_PIN(PORT_C, 8), GPIO_AF12 },
413 .dat1 = { GPIO_PIN(PORT_C, 9), GPIO_AF12 },
414 .dat2 = { GPIO_PIN(PORT_C, 10), GPIO_AF12 },
415 .dat3 = { GPIO_PIN(PORT_C, 11), GPIO_AF12 },
416#if MODULE_PERIPH_DMA
417 .dma = 6,
418 .dma_chan = 7,
419#endif
420 .irqn = SDMMC1_IRQn
421 },
422};
423
427#define SDMMC_CONFIG_NUMOF 1
428
430
443static const spi_conf_t spi_config[] = {
444 { /* Arduino connector */
445 .dev = SPI1,
446 .mosi_pin = GPIO_PIN(PORT_B, 5),
447 .miso_pin = GPIO_PIN(PORT_B, 4),
448 .sclk_pin = GPIO_PIN(PORT_A, 5),
449 .cs_pin = GPIO_PIN(PORT_A, 15),
450 .mosi_af = GPIO_AF5,
451 .miso_af = GPIO_AF5,
452 .sclk_af = GPIO_AF5,
453 .cs_af = GPIO_AF5,
454 .rccmask = RCC_APB2ENR_SPI1EN,
455 .apbbus = APB2,
456#if MODULE_PERIPH_DMA
457 .rx_dma = 0, /* DMA1 Channel 2 */
458 .rx_dma_chan = 1, /* CxS = 1 */
459 .tx_dma = 1, /* DMA1 Channel 3 */
460 .tx_dma_chan = 1, /* CxS = 1 */
461#endif
462 },
463#if MODULE_PERIPH_SPI_STMOD
464 { /* Pmod/STMod+ connector if solder bridges SB4, SB5, SB9 are closed */
465 .dev = SPI2,
466 .mosi_pin = GPIO_PIN(PORT_B, 15),
467 .miso_pin = GPIO_PIN(PORT_I, 2),
468 .sclk_pin = GPIO_PIN(PORT_I, 1),
469 .cs_pin = GPIO_PIN(PORT_G, 1),
470 .mosi_af = GPIO_AF5,
471 .miso_af = GPIO_AF5,
472 .sclk_af = GPIO_AF5,
473 .cs_af = GPIO_AF5,
474 .rccmask = RCC_APB1ENR1_SPI2EN,
475 .apbbus = APB1,
476#if MODULE_PERIPH_DMA
477 .rx_dma = 2, /* DMA1 Channel 4 */
478 .rx_dma_chan = 1, /* CxS = 1 */
479 .tx_dma = 3, /* DMA1 Channel 5 */
480 .tx_dma_chan = 1, /* CxS = 1 */
481#endif
482 },
483#endif
484};
485
486#define SPI_NUMOF ARRAY_SIZE(spi_config)
488
493static const timer_conf_t timer_config[] = {
494 {
495 .dev = TIM2,
496 .max = 0xffffffff,
497 .rcc_mask = RCC_APB1ENR1_TIM2EN,
498 .bus = APB1,
499 .irqn = TIM2_IRQn
500 },
501 {
502 .dev = TIM3,
503 .max = 0xffffffff,
504 .rcc_mask = RCC_APB1ENR1_TIM3EN,
505 .bus = APB1,
506 .irqn = TIM3_IRQn
507 },
508};
509
510#define TIMER_0_ISR isr_tim2
511#define TIMER_1_ISR isr_tim3
512
513#define TIMER_NUMOF ARRAY_SIZE(timer_config)
515
527static const uart_conf_t uart_config[] = {
528 { /* Virtual COM Port / ST-Link */
529 .dev = USART2,
530 .rcc_mask = RCC_APB1ENR1_USART2EN,
531 .rx_pin = GPIO_PIN(PORT_D, 6),
532 .tx_pin = GPIO_PIN(PORT_A, 2),
533 .rx_af = GPIO_AF7,
534 .tx_af = GPIO_AF7,
535 .bus = APB1,
536 .irqn = USART2_IRQn,
537#if MODULE_PERIPH_UART_HW_FC
538 .cts_pin = GPIO_UNDEF, /* CTS is not connected */
539 .rts_pin = GPIO_UNDEF, /* RTS is not connected */
540#endif
541 .type = STM32_USART,
542 .clk_src = 0, /* Use APB clock */
543#if MODULE_PERIPH_DMA
544 .dma = 4, /* DMA1 Channel 7 */
545 .dma_chan = 2, /* CxS = 2 */
546#endif
547 },
548 { /* Arduino connector RX/TX (D0/D1) */
549 .dev = LPUART1,
550 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
551 .rx_pin = GPIO_PIN(PORT_G, 8),
552 .tx_pin = GPIO_PIN(PORT_G, 7),
553 .rx_af = GPIO_AF8,
554 .tx_af = GPIO_AF8,
555 .bus = APB12,
556 .irqn = LPUART1_IRQn,
557#if MODULE_PERIPH_UART_HW_FC
558 .cts_pin = GPIO_UNDEF, /* CTS is not connected */
559 .rts_pin = GPIO_UNDEF, /* RTS is not connected */
560#endif
561 .type = STM32_LPUART,
562 .clk_src = 0, /* Use APB clock */
563#if MODULE_PERIPH_DMA
564 .dma = 5, /* DMA2 Channel 6 */
565 .dma_chan = 4, /* CxS = 4 */
566#endif
567 },
568
569#if !MODULE_PERIPH_SPI_STMOD
570 { /* Pmod/STMod+ connector if solder bridges SB6, SB7, SB8 are closed (default) */
571 .dev = USART1,
572 .rcc_mask = RCC_APB2ENR_USART1EN,
573 .rx_pin = GPIO_PIN(PORT_G, 10),
574 .tx_pin = GPIO_PIN(PORT_B, 6),
575 .rx_af = GPIO_AF7,
576 .tx_af = GPIO_AF7,
577 .bus = APB2,
578 .irqn = USART1_IRQn,
579#if MODULE_PERIPH_UART_HW_FC
580 .cts_pin = GPIO_PIN(PORT_G, 11),
581 .rts_pin = GPIO_PIN(PORT_G, 12),
582 .cts_af = GPIO_AF7,
583 .rts_af = GPIO_AF7,
584#endif
585 .type = STM32_USART,
586 .clk_src = 0, /* Use APB clock */
587#if MODULE_PERIPH_DMA
588 .dma = 2, /* DMA1 Channel 4 */
589 .dma_chan = 2, /* CxS = 2 */
590#endif
591 },
592#endif /* !MODULE_PERIPH_SPI_STMOD */
593};
594
595#define UART_0_ISR (isr_usart2)
596#define UART_1_ISR (isr_lpuart1)
597#define UART_2_ISR (isr_usart1)
598
599#define UART_NUMOF ARRAY_SIZE(uart_config)
601
602#ifdef __cplusplus
603}
604#endif
605
PORT_B
@ PORT_B
port B
Definition periph_cpu.h:44
PORT_G
@ PORT_G
port G
Definition periph_cpu.h:49
PORT_C
@ PORT_C
port C
Definition periph_cpu.h:45
PORT_F
@ PORT_F
port F
Definition periph_cpu.h:48
PORT_E
@ PORT_E
port E
Definition periph_cpu.h:47
PORT_A
@ PORT_A
port A
Definition periph_cpu.h:43
PORT_D
@ PORT_D
port D
Definition periph_cpu.h:46
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:42
PORT_H
@ PORT_H
port H
Definition periph_cpu.h:48
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition periph_cpu_common.h:50
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:274
sdmmc_config
static const sdmmc_conf_t sdmmc_config[]
SDMMC devices.
Definition periph_conf.h:146
fmc_bank_config
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
Definition periph_conf.h:196
fmc_config
static const fmc_conf_t fmc_config
FMC controller configuration.
Definition periph_conf.h:138
lcd_fmc_desc
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Definition periph_conf.h:359
cfg_usb_otg_fs.h
Common configuration for STM32 OTG FS peripheral.
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition cpu_gpio.h:103
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:106
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:105
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition cpu_gpio.h:110
GPIO_AF3
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:104
GPIO_AF12
@ GPIO_AF12
use alternate function 12
Definition cpu_gpio.h:114
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:108
STM32_LPUART
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition cpu_uart.h:38
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:37
APB1
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:78
APB2
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:79
FMC_BANK_CONFIG
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
Definition cpu_fmc.h:74
FMC_SRAM
@ FMC_SRAM
SRAM.
Definition cpu_fmc.h:340
FMC_BUS_WIDTH_16BIT
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
Definition cpu_fmc.h:352
FMC_BANK_1
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
Definition cpu_fmc.h:320
adc_conf_t
ADC device configuration.
Definition periph_cpu.h:374
dac_conf_t
DAC line configuration data.
Definition periph_cpu.h:300
dma_conf_t
DMA configuration.
Definition cpu_dma.h:31
fmc_bank_conf_t
Bank configuration structure.
Definition cpu_fmc.h:359
fmc_conf_t
FMC peripheral configuration.
Definition cpu_fmc.h:277
i2c_conf_t
I2C configuration structure.
Definition periph_cpu.h:295
lcd_fmc_desc_t
Descriptor of the FMC bank used for a LCD.
Definition lcd_fmc.h:48
pwm_conf_t
PWM device configuration.
Definition periph_cpu_common.h:319
sdmmc_conf_t
SDMMC slot configuration.
Definition periph_cpu.h:701
spi_conf_t
SPI device configuration.
Definition periph_cpu.h:333
timer_conf_t
Timer device configuration.
Definition periph_cpu.h:260
uart_conf_t
UART device configuration.
Definition periph_cpu.h:214
MiB
#define MiB(x)
A macro to return the bytes in x MiB.
Definition units.h:33