21#ifndef CONFIG_BOARD_HAS_LSE
22#define CONFIG_BOARD_HAS_LSE 1
25#include "periph_cpu.h"
27#include "cfg_rtt_default.h"
49#define DMA_0_ISR isr_dma1_channel2
50#define DMA_1_ISR isr_dma1_channel3
51#define DMA_2_ISR isr_dma1_channel4
52#define DMA_3_ISR isr_dma1_channel5
53#define DMA_4_ISR isr_dma1_channel7
54#define DMA_5_ISR isr_dma2_channel6
55#define DMA_6_ISR isr_dma2_channel4
57#define DMA_NUMOF ARRAY_SIZE(dma_config)
105#if !MODULE_PERIPH_DAC
115#define ADC_NUMOF ARRAY_SIZE(adc_config)
120#define VBAT_ADC ADC_LINE(7)
125#define VREFINT_ADC ADC_LINE(6)
135#ifndef VREFBUF_ENABLE
136#define VREFBUF_ENABLE (1)
152#if !MODULE_PERIPH_SPI
160#define DAC_NUMOF ARRAY_SIZE(dac_config)
173 .rcc_mask = RCC_AHB3ENR_FMCEN,
174#if MODULE_PERIPH_FMC_NOR_SRAM
210#if MODULE_PERIPH_FMC_16BIT
242 .address = 0x64000000,
248 .r_timing = { .addr_setup = 6,
250 .bus_turnaround = 1, },
259 .address = 0x60000000,
271 .r_timing = { .addr_setup = 1,
273 .bus_turnaround = 2, },
281#define FMC_BANK_NUMOF ARRAY_SIZE(fmc_bank_config)
290 .data_offset = 0x80000,
300#define LCD_FMC_NUMOF 1
320 .rcc_mask = RCC_APB1ENR1_I2C1EN,
321 .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1,
322 .irqn = I2C1_ER_IRQn,
336 .rcc_mask = RCC_APB1ENR1_I2C2EN,
337 .rcc_sw_mask = RCC_CCIPR_I2C2SEL_1,
338 .irqn = I2C2_ER_IRQn,
342#define I2C_0_ISR isr_i2c1_er
343#define I2C_1_ISR isr_i2c2_er
345#define I2C_NUMOF ARRAY_SIZE(i2c_config)
363 .rcc_mask = RCC_APB2ENR_TIM8EN,
365 { .pin =
GPIO_PIN(PORT_I, 6), .cc_chan = 1},
373 .rcc_mask = RCC_APB1ENR1_TIM4EN,
383 .rcc_mask = RCC_APB1ENR1_TIM5EN,
393#define PWM_NUMOF ARRAY_SIZE(pwm_config)
408 .rcc_mask = RCC_APB2ENR_SDMMC1EN,
427#define SDMMC_CONFIG_NUMOF 1
454 .rccmask = RCC_APB2ENR_SPI1EN,
463#if MODULE_PERIPH_SPI_STMOD
474 .rccmask = RCC_APB1ENR1_SPI2EN,
486#define SPI_NUMOF ARRAY_SIZE(spi_config)
497 .rcc_mask = RCC_APB1ENR1_TIM2EN,
504 .rcc_mask = RCC_APB1ENR1_TIM3EN,
510#define TIMER_0_ISR isr_tim2
511#define TIMER_1_ISR isr_tim3
513#define TIMER_NUMOF ARRAY_SIZE(timer_config)
530 .rcc_mask = RCC_APB1ENR1_USART2EN,
537#if MODULE_PERIPH_UART_HW_FC
550 .rcc_mask = RCC_APB1ENR2_LPUART1EN,
556 .irqn = LPUART1_IRQn,
557#if MODULE_PERIPH_UART_HW_FC
569#if !MODULE_PERIPH_SPI_STMOD
572 .rcc_mask = RCC_APB2ENR_USART1EN,
579#if MODULE_PERIPH_UART_HW_FC
595#define UART_0_ISR (isr_usart2)
596#define UART_1_ISR (isr_lpuart1)
597#define UART_2_ISR (isr_usart1)
599#define UART_NUMOF ARRAY_SIZE(uart_config)
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
static const sdmmc_conf_t sdmmc_config[]
SDMMC devices.
static const fmc_bank_conf_t fmc_bank_config[]
FMC Bank configuration.
static const fmc_conf_t fmc_config
FMC controller configuration.
static const lcd_fmc_desc_t lcd_fmc_desc[]
Descriptors of FMC banks used for LCDs.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF2
use alternate function 2
@ GPIO_AF5
use alternate function 5
@ GPIO_AF4
use alternate function 4
@ GPIO_AF8
use alternate function 8
@ GPIO_AF3
use alternate function 3
@ GPIO_AF12
use alternate function 12
@ GPIO_AF7
use alternate function 7
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
@ STM32_USART
STM32 USART module type.
@ APB1
Advanced Peripheral Bus 1.
@ APB2
Advanced Peripheral Bus 2.
#define FMC_BANK_CONFIG(n)
Gives the configuration of n-th bank.
@ FMC_BUS_WIDTH_16BIT
16 bit data bus width
@ FMC_BANK_1
Bank 1 is always available and used for NOR, PSRAM, SRAM.
ADC device configuration.
DAC line configuration data.
Bank configuration structure.
FMC peripheral configuration.
I2C configuration structure.
Descriptor of the FMC bank used for a LCD.
PWM device configuration.
SDMMC slot configuration.
SPI device configuration.
Timer device configuration.
UART device configuration.
#define MiB(x)
A macro to return the bytes in x MiB.